參數(shù)資料
型號(hào)： DS-S29804
廠商： Altera Corporation
英文描述： Stratix II EP2S60 DSP Development Board
中文描述： Stratix二EP2S60 DSP開發(fā)板
文件頁(yè)數(shù)： 32/52頁(yè)
文件大小： 3817K
代理商： DS-S29804
32
Preliminary
Altera Corporation
Stratix II EP2S60 DSP Development Board Data Sheet
Ethernet MAC/PHY (U1
6
)
The LAN91C111 (U16) is a mixed signal analog/digital device that
implements protocols at 10 Mbps and 100 Mbps. The control pins of U16
are connected to the Stratix II device so that user logic (e.g., the Nios II
processor) can access Ethernet via the RJ-45 connector (RJ1).
Table 24
lists the reference information for the Ethernet MAC/PHY.
CompactFlash Connector (CON1)
The CompactFlash connector header (CON1) enables hardware designs
to access a CompactFlash card. The following two access modes are
supported:
■
■
ATA (hot-swappable mode)
IDE (IDE hard-disk mode)
Most pins of CON1 connect to I/O pins on the FPGA. The following pins
have special connections:
■
Pin 13 of CON1 (VCC) is driven by a power MOSFET that is
controlled by an FPGA I/O pin. This allows the FPGA to control
power to the CompactFlash card for the IDE connection mode.
Pin 26 of CON1 (CD1#) is pulled up to 5V through a 10-K
resistor.
This signal is used to detect the presence of a CompactFlash card.
When the card is not present, the signal is pulled high through the
pull-up resistor.
Pin 41 of CON1 (RESET) is pulled up to 5V through a 10-K
resistor,
and is controlled by the EPM7128AE configuration controller. The
FPGA can cause the configuration controller to assert RESET, but the
FPGA does not drive this signal directly.
■
■
Table 24. Ethernet MAC/PHY Reference
Item
Description
Board reference
U16
Part Number
LAN91C111-NE
Device description
Ethernet MAC/PHY
Manufacturer
SMSC
Manufacturer web site
www.smsc.com
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