參數(shù)資料
型號(hào)： DS-S29804
廠商： Altera Corporation
英文描述： Stratix II EP2S60 DSP Development Board
中文描述： Stratix二EP2S60 DSP開(kāi)發(fā)板
文件頁(yè)數(shù)： 20/52頁(yè)
文件大?。?/td> 3817K
代理商： DS-S29804
20
Preliminary
Altera Corporation
Stratix II EP2S60 DSP Development Board Data Sheet
Figure 4
shows the pin-outs for the seven-segment display.
Figure 4. Pin-Out Diagram for the Dual Seven-Segment Display
A/D Converters
The Stratix II EP2S60 DSP development board has two 12-bit A/D
converters that produce samples at a maximum rate of 125 mega-samples
per second (MSPS). The A/D subsystem of the board has the following
features:
■
The data output format from each A/D converter to the Stratix II
device is in two’s complement format.
The circuit has a wideband, AC-coupled, differential input useful for
IF sampling. The analog inputs are transformer-coupled to the A/D
converter in order to create a balanced input. To maximize
performance, two transformers are used in series. The Analog
Devices data sheet for the AD9433 device describes the detailed
operation of this circuit.
Any required anti-aliasing filtering can be installed externally. If
needed, users can purchase in-line SMA filters from a variety of
manufacturers, such as Mini-Circuits (
www.minicircuits.com
).
■
■
1
The transformer-coupled AC circuit has a lower 3-dB frequency,
of approximately 1 MHz.
The clock signal that drives the A/D converters can originate from the
Stratix II device, the external clock input, or the on-board 100-MHz
oscillator. Jumper J3 controls which clock is used for ADC A and J4 is used
HEX_0A HEX_1A
HEX_0D HEX_0DP HEX_1D HEX_1DP
H
H
HEX_0G
HEX_1G
H
H
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