
56
8Bit Single Chip Microcontroller
        DMC73C167
 MOVP %10000000,   MSTS     ( BBUSY bi t has not been touched)
d) Write transfer (two byte data)
 MOVP %>88,   MDATA
 MOVP %10000000,    MCTL0
             Fri st byte of data to be sent
(ACT/-
/RSRT
/LODUTY
1
0
After the interrupt or polling check of the INT5_1F bit, clear it by writing 1 to the 
INT5_1C bit.
 MOVP %10000000,    MSTS
 MOVP %>AA,   MDATA
 MOVP %10000000,    MCTL0
             Cl ear INT5_1F bi t
             Second byte of data to be sent
(ACT/-
/RSRT
/LODUTY
After the interrupt or polling check of the INT5_1F bit, clear the INT5_1F bit.
 MOVP %10000000,  MSTS     (Clears INT5_1F bit)
e) Start condition generation and address transfer
To change the transfer direction or slave, a new cycle must be executed after the
current cycle is completed by generating a stop condition or invoking another start
condition.  To generate another start condition, the RSRT and BCM1 bits of MCTL0
should be set after a 4us delay to keep the set up time of the start condition.
The next data transfer cycle is for read, so reset bit 3 (MDIR).  To enable the start
action, set bit 7 (ACT) of MCTL0.
 MOVP %10100001,    MDATA
 MOVP %00100000,    MCTL0
             Reads data fromSl ave B
             Second byte of data to be sent
(ACT/-
/RSRT
/LODUTY
0
1
 WAITP BTJ OP  %00000010,  
 NOP
 NOP
 MOVP %>10100010,    MCTL0
              MCTL1,Wi ts unti l  I2C bus i f free
              One NOP w l l  produce a 2. 0 us del ay
After this instruction is executed, the I2C bus module will generate a start condition
and transfer 7 bit of address and 1 bit of direction information.  After the address 
/MDIR
/NACK
/BCM1
/BCM0)
0
0
0
0
0
/MDIR
/NACK
/BCM1
/BCM0)
1
0
0
0
0
0
0
/MDIR
/NACK
/BCM1
/BCM0)
0
0
0
0
0
(ACT/-
1
/RSRT
1
/LODUTY
/MDIR
/NACK
/BCM1
/BCM0)
0
0
0
1
0
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