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參數(shù)資料
| 型號： | DMC73C167 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁數(shù)： | 41/90頁 |
| 文件大?。?/td> | 742K |
| 代理商： | DMC73C167 |
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41
8Bit Single Chip Microcontroller
DMC73C167
5.5.1.7 Notes on Timer Usage
In Timer 1, the most significant byte (MSB) read-out latch is shared between the MSB of the
decrementer and the MSB of the capture latch to be sampled at one moment. The Timer 1
MSB read-out latch can be read from both P20 and P23. Reading the LSB of the decrementer
or capture latch will always update the contents of the read-out latch. In order to read correctly
the entire 16-bit value of the decrementer or capture latch, the LSB must be read first, which
will load the MSB read-out latch. The MSB read-out latch must be read and stored after
reading the LSB of either the decrementer or capture latch.
5.5.2 Timer 2 / Timer 3
Timer 2 and Timer 3 are 8-bit timers that contain a 2-bit prescaler and an 8-bit decrementer.
The clock source of Timer 2 is determined by the T2SRC bit of the T2CTL register (P25.5),
and the clock source of Timer 3 determined by the T3SRC bit of the T3CTL register (P27.6).
Setting the T2SRC or T3SRC bits to 0 selects the internally generated Fosc/4 clock and
places the timer in real-time clock mode. Setting the T2SRC bit to 1 selects the external clock
source and places Timer 2 in event counter mode. Setting the T3SRC bit to 1 selects the
Timer 2 underflow for the Timer 3 clock source, and makes Timer 2 and Timer 3 cascadable.
When 0 is written to the START bit, the timer chain is disabled or frozen at the current count
value. When 1 is written to the START bit, regardless of whether it was previously a 0 or a 1,
the prescaler and counter decrementers are loaded with the corresponding latch values,
and the timer/event counter operation begins.
When the prescaler and counter decrement through zero thogether, an interrupt flag is set,
and the prescaler and counter decrementers are immediately and automatically reloaded
with the corresponding latch values.
The interrupt levels generated by the timers are INT2_1 for Timer 2 and INT3_1 for Timer 3
Timer 2 and Timer 3 each have a respective associated 8-bit capture latch that captures
the current value of the counter whenever 8-bit capture latch that captures the current value
of the counter whenever Port A4 (INT3_0) for Timer 2 or Port A5 (INT5_0) for Timer 3 are
activated.
Figure 5-6. Timer 2 Block Diagram
￡￡á￡￡×￡￡
Pin A2
I/O Port A2/Event
Counter Clock Input
2- bit
Prescaler
Fosc/4
T2SRC
START(P25.7)
Capture Latch
External A4 Pin
INT3_0
Timer 2
Interrupt
(INT2_1)
Timer 3
Clock
8- bit
Decrementer
相關PDF資料 |
PDF描述 |
|---|---|
| DMC73C168 | 8Bit Single Chip Microcontroller |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DMC73C168 | 制造商:DAEWOO 制造商全稱:DAEWOO 功能描述:8Bit Single Chip Microcontroller |
| DMC757 | 制造商:Daniels Manufacturing Corporation (DMC) 功能描述:CONNECTOR |
| DMC-8/16-15 | 制造商:Brady Corporation 功能描述: |
| DMC-8/16-30 | 制造商:Brady Corporation 功能描述: |
| DMC80C49 | 制造商:DAEWOO 制造商全稱:DAEWOO 功能描述:CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER |
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