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參數(shù)資料
| 型號： | DMC73C167 |
| 英文描述： | 8Bit Single Chip Microcontroller |
| 中文描述： | 8位單芯片微控制器 |
| 文件頁數(shù)： | 35/90頁 |
| 文件大?。?/td> | 742K |
| 代理商： | DMC73C167 |
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35
8Bit Single Chip Microcontroller
DMC73C167
The interrupt flag (INTn-mF) is set to 1 by the INTn_m input. The INTnF flag becomes active
when INTnE is 1, then INTn occurs if the interrupt enable bit (I bit) of the status register is
set to 1.
Figure 5-2. External Interrupt Logic (n = 1, 3 or 5 ; m = 0)
To conserve the low power requirement, one low-power mode - the HALT MODE - is provided.
It is invoked by executing an IDLE instruction. An external interrupt will release the device from
the low-power mode depending on whether it is in the HALTmode. When an external interrupt
is first asserted, its level is gated into an interrupt flag. In order for an interrupt signal to be
detected, the pulse duration must be a minimum of five internal clock cycles.
The INTn Enable bit is used separately to individually mask interrupt levels, and must be set 1
for the interrupt to be recognized.
As Previously stated, all interrupt control bits are implemented in the IOCTL0, IOCTL1, IOCTL2,
IOCTL3, and IOCTL4 registers in the peripheral file. I/O instructions may simply read from and
write to each INTn Enable bit. By the INTn input, the interrupt flag is set to 1 at the falling or
rising edge and becomes active when an interrupt is enabled.The interrupt service routine is
executed after the currently executing instruction is completed. Once the interrupt has been
acknowledged by the CPU, the CPU then pushes the contents of the status register and the
program counter (MSB and LSB), respectively, onto the stack and makes zero the status
register (see Section 4.4). The corresponding vector address is loaded into the program
counter, and the interrupt service routine is executed. The external interrupts, INT1, INT3_0,
and INT5_0, have Schmitt-trigger inputs and can be used as zero-cross detectors.
Because the pins can be used as both external interrupt pins and general-purpose I/O pins,
the following points should be noted :
D
Q
Write
Read
Enable Latch
D
Q
Write
Read
Enable Latch
CL
R
S
Q
InmCLR
EXTINTn
(SCHIMITT)
SENSnm
InmFLG
Read
InmENA
INTnE
INTn
Happen
Interrupt Enable
(ST : Status Register)
Read
INTnF
INTn Enable
￡￡á￡￡×￡￡
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DMC73C168 | 8Bit Single Chip Microcontroller |
| DMC80C49 | CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER |
| DMCA1CHP | TRANSISTOR | MOSFET | ARRAY | N-CHANNEL | 20V V(BR)DSS | 50MA I(D) | CHIP |
| DMCB1CHP | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 50MA I(D) | CHIP |
| DMCB2CHP | TRANSISTOR | MOSFET | N-CHANNEL | 30V V(BR)DSS | 50MA I(D) | CHIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DMC73C168 | 制造商:DAEWOO 制造商全稱:DAEWOO 功能描述:8Bit Single Chip Microcontroller |
| DMC757 | 制造商:Daniels Manufacturing Corporation (DMC) 功能描述:CONNECTOR |
| DMC-8/16-15 | 制造商:Brady Corporation 功能描述: |
| DMC-8/16-30 | 制造商:Brady Corporation 功能描述: |
| DMC80C49 | 制造商:DAEWOO 制造商全稱:DAEWOO 功能描述:CMOS SINGLE-COMPONENT 8-BIT MICROCOMPUTER |
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