參數(shù)資料
型號: DM9801A
文件頁數(shù): 53/60頁
文件大?。?/td> 605K
代理商: DM9801A
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Final
Version: DM9801A-DS-F01
May 30, 2001
53
MII-1M Receive Nibble Timing Parameters
Symbol
t
RXs
Parameter
Min.
10
Typ.
Max.
Unit
ns
Conditions
RXD[0:3), RX_DV, RX_ER
Setup To RX_CLK High
RXD[0:3], RX_DV, RX_ER Hold
From RX_CLK High
HN
+/-
In To RXD[0:3] Out (Rx
Latency)
CRS Asserted To RXD[0:3],
RX_DV, RX_ER
CRS De-asserted To RXD[0:3],
RX_DV, RX_ER
HN
+/-
In To CRS Asserted
HN
+/-
Quiet To CRS De-asserted
t
RXh
10
ns
t
RXpd
154
us
t
1
153
us
t
2
0
ns
t
3
t
4
474
20.1
ns
us
GPSI-1M Clock Timing Parameters
Symbol
GPSI (General Purpose Serial Interface)
Idle (excluding IFG time)
t
PWH
STDCLK/SRDCLK Pulse Width
High
t
PWL
STDCLK/SRDCLK Pulse Width
Low
Preamble (first 64 bits of TX MAC frame)
t
TPWH
STDCLK Pulse Width High
t
TPWL
STDCLK Pulse Width Low
t
RPWH
SRDCLK Pulse Width High
t
RPWL
SRDCLK Pulse Width Low
Data (throughout the data phase)
t
PWH
STDCLK/SRDCLK Pulse Width
High
t
PWL
STDCLK/SRDCLK Pulse Width
Low
IFG (96 bit times following CRS falling edge)
t
PWH
STDCLK/SRDCLK Pulse Width
High
t
PWL
STDCLK/SRDCLK Pulse Width
Low
Notes: 1) During AID interval, SRDCLK and STDCLK stop for up to 140 us.
2) During Preamble state, SRDCLK stays at Low.
Parameter
Min.
Typ.
Max.
Unit
Conditions
468
ns
115.3
ns
118
115.3
-
-
ns
ns
ns
ns
115.3
ns
115.3
8.17
us
115.3
ns
118
ns
115.3
ns
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