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參數(shù)資料
| 型號： | DM9801A |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 605K |
| 代理商： | DM9801A |
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DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
34
Final
Version: DM9801A-DS-F01
May 30, 2001
SPI Serial Management Register Map (INTFSEL = 1, GPSI Mode)
Register
Address
1-0
CNTRL
3-2
STATUS
5-4
IMASK
7-6
ISTAT
9-8
TX_PCOM_LO
11-10
TX_PCOM_HI
13-12
RX_PCOM_LO
15-14
RX_PCOM_HI
17-16
PEAK_NOISE
19-18
NOISE_CNTRL_A
21-20
NOISE_CNTRL_B
22
FWENA
Register Name
Access
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Default
Value
0x1005
0x0005
0x0000
0x0080
0x0000
0x0000
0x0000
0x0000
0xFF07
0xC207
0x00F4
0x00
Description
Control Registers
Status Registers
Interrupt Mask Registers
Interrupt Status Registers
Transmit PHY Communication Low Word
Transmit PHY Communication High Word
Receive PHY Communication Low Word
Receive PHY Communication High Word
PEAK Level and Noise Level Registers
Noise Ceiling and Noise Floor Registers
Noise Events and Noise Attack Registers
Four Wire Enable and Link Disable Registers
25
AID_ADDRESS
AID_CNTRL
SYM_CNTRL
TX_SIG_CNTRL
RW
RW
RW
0x00
0x4014
0x1C2C
0x4404
AID Address Register
AID Interval and AID ISBI Registers
DATA ISBI Control Registers
Transmit Pulse Control Registers
27-26
29-28
31-30
SPI Serial Management Control Register - Register 0 (INTFSEL = 1, GPSI Mode)
Bit
Bit Name
Default
0.7
AID_ADR_NEG
0,RW
Description
AID Address Negotiation:
1= Stop AID address negotiation
0= Normal operation
Clear Noise Event Register:
1= Clear the Noise Event Register
0= Normal operation
Slice Level Adaptation:
1= Slice level adaptation is disabled (stopped).
0= Slice level adaptation is enabled
Power Down:
Writing a 1 to this bit will cause DM9801A to enter Sleep mode
and power down all circuits except the oscillator and clock
generator circuit. To exit Sleep mode, write 0 to this bit position.
The prior configuration will be retained when the sleep state is
terminated, but the state machine will be reset
Reserved:
This bit must be written as 0
Speed:
1= high speed
0= low speed
This bit indicates the network speed is set to high as selected
by the status of the SPDSEL pin during power-up/reset.
Power:
1= high power
0= low power
This bit indicates the network power is set to high as selected
by the status of the PWRSEL pin during power-up/reset.
0.6
CLR_NS_EVNT
0,RW
0.5
SLC_LVL_ADP
0,RW
0.4
PWR_DWN
0,RW
0.3
Reserved
0,RW
0.2
Speed
1,RW
0.1
POWER
0,RW
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相關(guān)代理商/技術(shù)參數(shù) |
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