參數(shù)資料
型號(hào)： DM93L34
文件頁數(shù)： 9/158頁
文件大?。?/td> 2668K
代理商： DM93L34
TL/F/6601
9
June 1989
9301/DM9301
1-of-10 Decoders
General Description
These BCD-to-decimal decoders consist of eight inverters
and ten 4-input NAND gates. The inverters are connected in
pairs to make BCD input data available for decoding by the
NAND gates. Full decoding of valid input logic ensures that
all outputs remain ‘‘OFF’’ for all invalid input conditions.
These circuits provide familiar TTL inputs and outputs which
are compatible for use with other TTL and DTL circuits. DC
noise margins are typically 1V and power dissipation is typi-
cally 125 mW. The diode-clamped, buffered inputs repre-
sent only one normalized Series 54/74 load.
Features
Y
Direct replacement for Signetics 8252
Y
Diode-clamped inputs
Y
All outputs are high for invalid BCD input conditions
Y
Typical power dissipation 125 mW
Y
Typical propagation delay 20 ns
Connection Diagram
Dual-In-Line Package
TL/F/6601–1
Order Number 9301DMQB, 9301FMQB or DM9301N
See NS Package Number J16A, N16E or W16A
Function Table
No.
BCD Inputs
Decimal Outputs
D
C
B
A
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
L
H
L
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
5
6
7
8
9
L
L
L
H
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
L
I
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
N
V
A
L
I
D
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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