參數資料
型號: DM93L34
文件頁數: 147/158頁
文件大?。?/td> 2668K
代理商: DM93L34
Switching Characteristics
V
CC
e a
5.0V, T
A
e a
25
§
C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
C
L
e
15 pF
Units
Min
Max
t
PLH
t
PHL
Propagation Delay
E to Q
n
45
42
ns
t
PLH
t
PHL
Propagation Delay
D to Q
n
65
45
ns
t
PLH
t
PHL
Propagation Delay
A
n
to Q
n
66
66
ns
t
PHL
Propagation Delay
CL to Q
n
55
ns
Functional Description
The 93L34 has four modes of operation which are shown in
the Mode Select Table. In the addressable latch mode, data
on the data line (D) is written into the addressed latch. The
addressed latch will follow the Data input with all non-ad-
dressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous state and
are unaffected by the data or address inputs. To eliminate
the possibility of entering erroneous data into the latches,
the Enable should be held HIGH while the Address lines are
changing. In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the state of the D input with
all other outputs in the LOW state. In the clear mode all
outputs are LOW and unaffected by the address and data
inputs. When operating the 93L34 as an addressable latch,
changing more than one bit of the address could impose a
transient wrong address. Therefore, this should only be
done while in the memory mode.
Mode Select Table
E
CL
Mode
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH 8-Channel Demultiplexer
Clear
3
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