參數(shù)資料
型號： DM93L22
文件頁數(shù)： 31/158頁
文件大?。?/td> 2668K
代理商： DM93L22
TL/F/6606
9
June 1989
9316/DM9316 Synchronous 4-Bit Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The 9316 is a 4-bit binary counter. The carry output
is decoded by means of a NOR gate, thus preventing spikes
during the normal counting mode of operation. Synchronous
operation is provided by having all flip-flops clocked simulta-
neously so that the outputs change coincident with each
other when so instructed by the count-enables inputs and
internal gating. This mode of operating eliminates the output
counting spikes which are normally associated with asyn-
chronous (ripple clock) counters. A buffered clock input trig-
gers the four flip-flops on the rising (positive-going) edge of
the clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse regardless of the levels of the enable
input. Low-to-high transitions at the load input are perfectly
acceptable regardless of the logic levels on the clock or
enable inputs. The clear function is asynchronous and a low
level at the clear input sets of the flip-flop outputs low re-
gardless of the levels of clock, load, or enable inputs.
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output. Both count-
enable inputs (P and T) must be high to count, and input T is
fed-forward to enable the ripple carry output. The ripple car-
ry output thus enabled will produce a high-level output pulse
with a duration approximately equal to the high-level portion
of the Q
A
output. This high-level overflow ripple carry pulse
can be used to enable successive cascaded stages. High-
to-low level transitions at the enable P or T inputs may occur
regardless of the logic level in the clock.
Features
Y
Internal look-ahead for fast counting
Y
Carry output for n-bit cascading
Y
Synchronous counting
Y
Load control line
Y
Diode-clamped inputs
Y
Typical clock frequency 35 MHz
Y
Pin-for-pin replacements popular 54/74 counters
5416A/7416A (binary)
Y
Alternate Military/Aerospace device (9316) is available.
Contact a National Semiconductor Sales Office/Distrib-
utor for specifications.
Connection Diagram
Dual-In-Line Package
TL/F/6606–1
Order Number 9316DMQB, 9316FMQB, DM9316J
DM9316W or DM9316N
See NS Package Number J16A, N16E or W16A
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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DM93L34 制造商:未知廠家 制造商全稱:未知廠家 功能描述:
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