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參數(shù)資料
| 型號： | DM93L22 |
| 文件頁數(shù)： | 106/158頁 |
| 文件大小： | 2668K |
| 代理商： | DM93L22 |
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Functional Description
The 93L10 counts modulo-10 in the BCD (8421) sequence.
From state 9 (HLLH) it increments to state 0 (LLLL). The
93L16 counts modulo-16 in binary sequence. From state 15
(HHHH) it increments to state 0 (LLLL). The clock inputs of
all flip-flops are driven in parallel through a clock buffer.
Thus all changes of the Q outputs (except due to Master
Reset) occur as a result of, and synchronous with, the LOW-
to-HIGH transition of the CP input signal. The circuits have
four fundamental modes of operation, in order of prece-
dence: asynchronous reset, parallel load, count-up and
hold. Four control inputsDMaster Reset (MR), Parallel En-
able (PE), Count Enable Parallel (CEP) and Count Enable
Trickle (CET)Ddetermine the mode of operation, as shown
in the Mode Select Table. A LOW signal on MR overrides all
other inputs and asynchronously forces all outputs LOW. A
LOW signal on PE overrides counting and allows informa-
tion on the Parallel Data (P
n
) inputs to be loaded into the
flip-flops on the next rising edge of CP. With PE and MR
HIGH, CEP and CET permit counting when both are HIGH.
Conversely, a LOW signal on either CEP or CET inhibits
counting.
The 93L10 and 93L16 contain masterslave flip-flops which
are ‘‘next-state catching’’ because of the JK feedback. This
means that when CP is LOW, information that would change
the state of a flip-flop, whether from the counting logic or
the parallel entry logic if either mode is momentarily en-
abled, enters the master and is locked in. Thus to avoid
inadvertently changing the state of a master latch, and the
subsequent transfer of the erroneous information to the
slave when the clock rises, it is necessary to insure that
neither the counting mode, nor the parallel entry mode is
momentarily enabled while CP is LOW.
The Terminal Count (TC) output is HIGH when CET is HIGH
and the counter is in its maximum count state (9 for the
decade counters, 15 for the binary countersDfully decoded
in both types). To implement synchronous multistage coun-
ters, the TC outputs can be used with the CEP and CET
inputs in two different ways. These two schemes are shown
in Figures a and b. The TC output is subject to decoding
spikes due to internal race conditions and is therefore not
recommended for use as a clock or asynchronous reset for
flip-flops, counters or registers. If a decade counter is preset
to an illegal state, or assumes an illegal state when power is
applied, it will return to the normal sequence within two
counts, as shown in the state diagrams.
MULTISTAGE COUNTING
The ‘10/‘16 counters may be cascaded to provide multi-
stage synchronous counting. Two methods commonly used
to cascade these counters are shown in Figures a and b.
In multistage counting, all less significant stages must be at
their terminal count before the next more significant counter
is enabled. The ‘10/‘16 internally decodes the terminal
count condition and ‘‘ANDs’’ it with the CET input to gener-
ate the terminal count (TC) output. This arrangement allows
one to perform series enabling by connecting the TC output
(enable signal) to the CET input of the following stage, Fig-
ure a. The setup requires very few interconnections, but has
the following drawback: since it takes time for the enable to
ripple through the counter stages, there is a reduction in
maximum counting speed. To increase the counting rate, it
is necessary to decrease the propagation delay of the TC
signal, which is done in the second method.
The scheme illustrated inFigure b permits multistage count-
ing, limited by the fan-out of the terminal count. The CEP
input of the ‘10/‘16 is internally ‘‘ANDed’’ with the CET input
and as a result, both must be HIGH for the counter to be
enabled. The CET inputs are connected as before except
for the second stage. There the CET input is left floating and
is therefore HIGH. Also, all CEP inputs are connected to the
terminal output of the first stage. The advantage of this
method is best seen by assuming all stages except the sec-
ond and last are in their terminal condition. As the second
stage advances to its terminal count, an enable is allowed
to trickle down to the last counter stage, but has the full
cycle time of the first counter to reach it. Then as the TC of
the first stage goes active (HIGH), all CEP inputs are activat-
ed, allowing all stages to count on the next clock.
4
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