- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376802 > DM9102AF (Electronic Theatre Controls, Inc.) Single Chip Fast Ethernet NIC controller PDF資料下載
參數(shù)資料
| 型號(hào)： | DM9102AF |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single Chip Fast Ethernet NIC controller |
| 中文描述： | 單芯片快速以太網(wǎng)網(wǎng)卡控制器 |
| 文件頁數(shù)： | 56/77頁 |
| 文件大?。?/td> | 459K |
| 代理商： | DM9102AF |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁當(dāng)前第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁
DM9102A
Single Chip Fast Ethernet NIC controller
56
Final
Version: DM9102A-DS-F03
August 28, 2000
Network Function
1. Overview
This chapter will introduce the normal state machine
operation and MAC layer management like collision backoff
algorithm. In transmit mode, the DM9102A initiates a DMA
cycle to access data from a transmit buffer. It prefaces the
data with the preamble, the SFD pattern, and it appends a
32-bit CRC. In receive mode, the data is de-serialized by
receive mechanism and fed into the internal FIFO. For
detailed process, please see below.
2. Receive Process and State Machine
a. Reception Initiation
As a preamble being detected on receive data lines, the
DM9102A synchronizes itself to the data stream during the
preamble and waits for the SFD. The synchronization
process is based on byte boundary and the SFD byte is
10101011. If the DM9102A receives a 00 or a 11 after the
first 8 preamble bits and before receiving the SFD, the
reception process will be terminated.
b. Address Recognition
After initial synchronization, the DM9102A will recognize the
6-byte destination address field. The first bit of the
destination address signifies whether it is a physical address
(=0) or a multicast address (=1). The DM9102A filters the
frame based on the node address of receive address filter
setting. If the frame passes the filter, the subsequent serial
data will be delivered into the host memory.
c. Frame Decapsulation
The DM9102A checks the CRC bytes of all received frames
before releasing the frame along with the CRC to the host
processor.
3. Transmit Process and State Machine
a. Transmission Initiation
Once the host processor prepares a transmit descriptor for
the transmit buffer, the host processor signals the DM9102A
to take it. After the DM9102A has been notified of this
transmit list, the DM9102A will start to move the data bytes
from the host memory to the internal transmit FIFO. When
the transmit
FIFO is adequately filled to the programmed threshold level,
or when there is a full frame buffered into the transmit FIFO,
the DM9102A begins to encapsulate the frame. The
transmit encapsulation is performed by the transmit state
machine, which delays the actual transmission onto the
network until the network has been idle for a minimum inter
frame gap time.
b. Frame Encapsulation
The transmit data frame encapsulation stream consists of
two parts: Basic frame beginning and basic frame end. The
former contains 56 preamble bits and SFD, the later, FCS.
The basic frame read from the host memory includes the
destination address, the source address, the type/length
field, and the data field. If the data field is less than 46 bytes,
the DM9102A will pad the frame with pattern up to 46 bytes.
c. Collision
When concurrent transmissions from two or more nodes
occur (termed; collision), the DM9102A halts the
transmission of data bytes and begins a jam pattern
consisting of AAAAAAAA. At the end of the jam
transmission, it begins the backoff wait time. If the collision
was detected during the preamble transmission, the jam
pattern is transmitted after completing the preamble. The
backoff process is called truncated binary exponential
backoff. The delay is a random integer multiple of slot times.
The number of slot times of delay before the Nth
retransmission attempt is chosen as a uniformly distributed
random integer in the range:
0
≤
r < 2k
k = min ( n, N ) and N=10
4. Physical Layer Overview:
The DM9102A provides 100M/10Mbps dual port operation.
It provides a direct interface either to Unshielded Twisted
pair Cable UTP5 for 100BASE-TX Fast Ethernet, or
UTP5/UTP3 Cable for 10BASE-T Ethernet. In physical level
operation, it consists of the following blocks:
PCS
Clock generator
NRE/NREI, MLT-3 encoder/decoder and driver
MANCHESTER encoder/decoder
10BASE-T filter and driver
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DM9102AT | Single Chip Fast Ethernet NIC controller |
| DM9108APPLICATIONENGINEERINGNOTESONE | DM9108 Application Engineering notes one |
| DM9108APPLICATIONENGINEERINGNOTESTHREE | DM9108 Application Engineering notes three |
| DM9108APPLICATIONENGINEERINGNOTESTWO | DM9108 Application Engineering notes two |
| DM9161A | 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DM9102AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller |
| DM9102D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER |
| DM9102DE | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
| DM9102DEP | 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes |
| DM9102H | 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。