參數(shù)資料
型號(hào)： DM9102AF
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁(yè)數(shù)： 53/77頁(yè)
文件大?。?/td> 459K
代理商： DM9102AF
DM9102A
Single Chip Fast Ethernet NIC controller
Bit 1: FUE, FIFO Underrun Error
It is set to indicate the transmission aborted due to transmit
FIFO underrun condition.
Final
Version: DM9102A-DS-F03
August 28, 2000
53
Bit 0: DF, Deferred
It is set to indicate the frame is deferred before ready to
transmit.
TDES1: Transmit buffer control and buffer size
Bit 31: CI, Completion Interrupt
It is set to enable transmit interrupt after the present frame
has been transmitted. It is valid only when TDES1<30> is
set or when it is a setup frame.
31
30
29
28
27
26
25
24
23
22
21 ~ 11
10 ~ 0
CI
ED
BD
FMB1 SETF CAD
///
CE
PD FMB0
Buffer Length
Bit 30: ED, Ending Descriptor
It is set to indicate the pointed buffer contains the last
segment of a frame.
Bit 29: BD, Begin Descriptor
It is set to indicate the pointed buffer contains the first
segment of a frame.
Bit 28: FMB1, Filtering Mode Bit 1
This bit is used with FMB0 to indicate the filtering type when
the present frame is a setup frame.
Bit 27: SETF, Setup Frame
It is set to indicate the current frame is a setup frame.
Bit 26: CAD, CRC Append Disable
It is set to disable the CRC appending at the end of the
transmitted frame. Valid only when TDES1<29> is set.
Bit 24: CE, Chain Enable
Must be “1”.
Bit 23: PD, Padding Disable
This bit is set to disable the padding field for a packet shorter
than 64 bytes.
Bit 22: FMB0, Filtering Mode Bit 0
This bit is used with FMB1 to indicate the filtering type when
the present frame is a setup frame.
FMB1 FMB0 Filtering Type
0 0 Perfect Filtering
0 1 Hash Filtering
1 0 Inverse Filtering
1 1 Hash-Only Filtering.
Bit 10-0: Buffer 1 length
Indicates the size of buffer in Chain type structure.
TDES2: Buffer Starting Address indicates the physical starting address of buffer.
31
0
Buffer Address 1
TDES3: Address indicates the next descriptor starting address
Indicates the physical starting address of the chained descriptor under the Chain descriptor structure.
This address must be eight word alignment.
31
0
Buffer Address 2
Initialization Procedure
After hardware or software reset, transmit and receive
processes are placed in the state of STOP. The DM9102A
相關(guān)PDF資料
PDF描述
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
DM9108APPLICATIONENGINEERINGNOTESTWO DM9108 Application Engineering notes two
DM9161A 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DM9102AT 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102D 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱(chēng):DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102DEP 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes
DM9102H 制造商:DAVICOM 制造商全稱(chēng):DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
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