參數(shù)資料
型號： DM9102AF
廠商： Electronic Theatre Controls, Inc.
英文描述： Single Chip Fast Ethernet NIC controller
中文描述： 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁數(shù)： 46/77頁
文件大?。?/td> 459K
代理商： DM9102AF
DM9102A
Single Chip Fast Ethernet NIC controller
1=100BASE-TX Half Duplex supported by the link partner
0=100BASE-TX Half Duplex not supported by the link partner
5.6
10_FDX
0, RO
10BASE-T Full Duplex Support:
1=10BASE-T Full Duplex supported by the link partner 0=10BASE-T Full
Duplex not supported by the link partner
5.5
10_HDX
0, RO
10BASE-T Support:
1=10BASE-T Half Duplex supported by the link partner
0=10BASE-T Half Duplex not supported by the link partner
5.4-5.0
Selector
<00000>,
RO
Link partner’s binary encoded protocol selector
46
Final
Version: DM9102A-DS-F03
August 28, 2000
Protocol Selection Bits:
Auto-Negotiation Expansion Register (ANER) – 6
Bit
Name
Reserved
Default
0, RO
Description
6.15-6.5
Reserved:
Write as 0, ignore on read
0, RO/LH Local Device Parallel Detection Fault:
PDF=1: A fault detected via parallel detection function.
PDF=0: No fault detected via parallel detection function
0, RO
Link Partner Next Page Able:
LP_NP_ABLE=1: Link partner, next page available
LP_NP_ABLE=0: Link partner, no next page
0,RO/P
Local Device Next Page Able:
NP_ABLE=1: DM9102A, next page available
NP_ABLE=0: DM9102A, no next page
DM9102A does not support this function, so this bit is always 0.
0, RO/LH New Page Received:
A new link code word page received. This bit will be automatically
cleared when the register (Register 6) is read by management
0, RO
Link Partner Auto-negotiation Able:
A “1” in this bit indicates that the link partner supports Auto-negotiation.
6.4
PDF
6.3
LP_NP_ABLE
6.2
NP_ABLE
6.1
PAGE_RX
6.0
LP_AN_ABLE
DAVICOM Specified Configuration Register (DSCR) - 10h
Bit
Name
Reserved
F_LINK_100
Default
0, RO
0, RW
Description
16.15:16.8
16.7
Reserved
Force Good Link in 100Mbps:
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This bit is useful for diagnostic purposes.
Reserved
Reset State Machine:
When writes 1 to this bit, all state machines of PHY will be reset. This bit is
self-clear after reset is completed.
MF Preamble Suppression Control:
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
16.6:16.4
16.3
Reserved
SMRST
0,RO
0,RW
16.2
MFPSC
0,RW
相關PDF資料
PDF描述
DM9102AT Single Chip Fast Ethernet NIC controller
DM9108APPLICATIONENGINEERINGNOTESONE DM9108 Application Engineering notes one
DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
DM9108APPLICATIONENGINEERINGNOTESTWO DM9108 Application Engineering notes two
DM9161A 10/100 MBPS FAST ETHEMET PHYSICAL LAYER SINGLE CHIP TRANSCEIVER
相關代理商/技術參數(shù)
參數(shù)描述
DM9102AT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single Chip Fast Ethernet NIC controller
DM9102D 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SINGLE CHIP FAST ETHEMET NIC CONTROLLER
DM9102DE 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
DM9102DEP 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 1 制造商:DAVICOM 功能描述:IC ENET CNTRL 10/100M PHY 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP 制造商:DAVICOM 功能描述:IC, ENET CNTRL, 10/100M PHY, 128LQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:2.375V; Supply Voltage Max:2.625V; Digital IC Case Style:LQFP; No. of Pins:128; Interface Type:PCI; Operating Temperature Min:0C;;RoHS Compliant: Yes
DM9102H 制造商:DAVICOM 制造商全稱:DAVICOM 功能描述:Single Chip Fast Ethernet NIC Controller
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