參數(shù)資料
型號(hào): DM9102AF
廠商: Electronic Theatre Controls, Inc.
英文描述: Single Chip Fast Ethernet NIC controller
中文描述: 單芯片快速以太網(wǎng)網(wǎng)卡控制器
文件頁(yè)數(shù): 22/77頁(yè)
文件大?。?/td> 459K
代理商: DM9102AF
DM9102A
Single Chip Fast Ethernet NIC controller
22
Final
Version: DM9102A-DS-F03
August 28, 2000
Interrupt & Latency Configuration (xxxxxx3c - PCIINT)
31
16
15
0
8
7
23
24
MAX_LAT
MIN_GNT
INT_PIN
INT_LINE
Maximum Latency Timer
Minimum Grant
Interrupt Pin
Interrupt Line
Bit
31:24
23:16
Default
28h
14h
Type
RO
RO
Description
Maximum Latency Timer that can be sustained (Read Only and Read As 28h)
Minimum Grant
Minimum Length of a Burst Period (Read Only and
Read As 14h)
Interrupt Pin read as 01h to indicate INTA#
Interrupt Line that Is Routed to the Interrupt Controller
The value depends on mainboard.
15:8
7:0
01h
XXh
RO
RW
Device Specific Configuration Register (xxxxxx40h- PCIUSR)
31 30 29
16 15
8
0
Reserved
27 26
28
7
25 24 23
Device Specific
Link Event enable/disable
Sample Frame Event enable/disable
Magic Packet Event enable/disable
Link Event Status
Sample Frame Event Status
Magic Packet Event Status
Device Specific
Reserved
Bit
31
30
29
28
27
26
25
Default
0
0
0
0
0
0
0
Type
RW
RW
RW
RW
RW
RO
RO
Description
Device Specific Bit (sleep mode)
Device Specific Bit (snooze mode)
When set enable Link Status Change Wake-up Event
When set enable Sample Frame Wake-up Event
When set enable Magic Packet Wake-up Event
When set, indicates link change and Link Status Change Event occurred
When set, indicates the sample frame is received and Sample Frame Event
occurred
When set, indicates the Magic Packet is received and Magic packet Event occurred
Reserved Bits Read As 0
Device Specific
Reserved Bits Read As 0
24
0
RO
RO
RW
RO
23:16
15:8
7:0
00h
00h
00h
相關(guān)PDF資料
PDF描述
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DM9108APPLICATIONENGINEERINGNOTESTHREE DM9108 Application Engineering notes three
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參數(shù)描述
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