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參數(shù)資料
| 型號(hào)： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設(shè)備 |
| 文件頁數(shù)： | 9/25頁 |
| 文件大小： | 360K |
| 代理商： | DLKPC192S |
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SLLS536
–
AUGUST 2002
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
reception
XSBI receive data bus
Connection from the PMA to the DLKPC192S is via a 16-bit-wide LVDS parallel bus. Data is received on the
RXP[0:15]/RXN[0:15] terminals and is clocked in using the RXCP/RXCN clock. A 100-
on-chip termination
resistor is placed differentially at each LVDS input pair. The rising edge of RXCP/RSCN is used to latch the data
as shown in Figure 7. Please note, the phase relationship is such that the positive side of the differential clock
needs to rise
in the middle of the data.
This is in contrast to the transmit XSBI interface. At that interface, the
positive side of the clock is in phase with the data. To successfully loop the transmit path to the receive path
of this PCS device you must attach TXCP to RXCN and TXCN to RXCP. Detailed timing information is provided
later in the
XSBI
paragraph of the
timing
—
reference clock
section.
RXCP/
RXCN
RXP[0:15]
RXN[0:15]
t(HOLD)
t(SETUP)
Figure 7. XSBI Receive Input Timing Waveform
receive gearbox
While the transmit gearbox only performs the task of converting 66-bit data to be transported on the 16-bit XSBI
bus, the receive gearbox has more to do than just the reverse of this function. The receive gearbox must also
determine where within the incoming data stream the boundaries of the 66-bit code words are. The receive
gearbox has the responsibility of initially synchronizing the header field of the code words and continuously
monitoring the ongoing synchronization. After obtaining synchronization to the incoming data stream, the
gearbox assembles 66-bit code words and presents these to the 66b/64b decoder. While the effective bit rate
of the 66-bit data stream is equal to the effective bit rate of the 16-bit XSBI bus, the clock rates of the two buses
are of different frequencies, thus the need for the gearbox.
66b/64b decode
The data received from the XSBI bus is encoded data. The DLKPC192S decodes the data received using the
66b/64b decoding algorithm defined in the proposed IEEE 802.3ae standard. The DLKPC192S creates
consecutive 36-bit data words from the encoded 66-bit code words for transfer over the XGMII interface to the
MAC. The information for the two XGMII transfers includes 64 bits of data and 8 bits of control information. Not
all code words are valid. Invalid code words are handled by the 66b/64b decode block and appropriate error
handling is provided, as defined in the proposed IEEE 802.3ae standard.
The decoding algorithm is fully described within the proposed IEEE 802.3ae standard. It includes two steps,
a descrambling step which unscrambles 64 bits of the 66-bit code word, and a decoding step which converts
the 66 bits of data received to two sets of data, each consisting of 32 bits of data and 4 bits of control information.
These words are sent to the receive FIFO block. The descrambler reverses the scrambling algorithm x
57
+x
39
+1.
receive FIFO
The receive FIFO provides sufficient buffer to compensate for both short-term clock-phase jitter and long-term
frequency differences between the input of data from the XSBI interface and the output of data over the XGMII
interface. Logic within the receive FIFO provides the ability for the insertion or deletion of characters when the
transfer rate between the interfaces differs. If not for this ability, FIFO overruns or underruns could occur and
cause corruption of data. The logic within the receive FIFO performs inserts or deletes, when necessary, in such
a way as to prevent corruption of Ethernet packets being transferred through the DLKPC192S.
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