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參數(shù)資料
| 型號： | DLKPC192S |
| 英文描述： | 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device |
| 中文描述： | 10Gbps的以太網(wǎng)物理編碼子層（PCS）設備 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大小： | 360K |
| 代理商： | DLKPC192S |
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SLLS536
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AUGUST 2002
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description (continued)
MDIO management interface
The DLKPC192S supports the management interface (MDIO) as defined in the IEEE 802.3-2000 Ethernet
standard. (Note: This is not the same as defined in the IEEE 802.3ae standard, clause 45.) The DLKPC192S
supports PCS registers as defined in this specification. At the time of definition of the DLKPC192S, the register
set for PCS devices was in flux so a suitable definition was selected and implemented.
The MDIO interface allows register-based management and control. Normal operation of the device is possible
without use of this interface because all of the essential signals necessary for operation are accessible via the
device terminals. However, some additional features are accessible only through the MDIO.
The MDIO interface provides a means of external access to the registers within the DLKPC192S. Access is via
two I/O signals: an input clock to the device and a bidirectional data signal. Commands and data are transferred
one bit at a time by placing a bit value on the data line and clocking that bit using the clock line. Commands
consist of two basic types: read and write. Except during a portion of a read command as described below, the
data line is configured as an input to the DLKPC192S.
The MDIO interface is a daisy-chained interface and often connects multiple devices such as the DLKPC192S
to a processor. The result is that other devices may reside on the MDIO bus that is connected to the
DLKPC192S. Each command sent over the MDIO interface includes an address field that determines the device
on the MDIO interface for which the command is intended. The DLKPC192S has five input terminals that
determine its MDIO address (DVAD0 through DVAD4).
If no commands are being transferred, the data line is held in the high state with pullups to ensure a 1 is seen
on the interface. The clock line can be continuously running or it may be idled (high or low) to conserve power
and then restarted to transfer a new command, provided minimum pulse duration timings are maintained.
The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference (MDC).
The protocol for reading from the internal registers is shown in Figure 10 The protocol for writing to the internal
registers is shown in Figure 11. Detailed timing information is provided later in this document. The following
paragraphs explain the two diagrams.
The sending device should send 32 or more consecutive 1s prior to beginning a new command. These 1s are
known as the preamble. The DLKPC192S requires only two 1s between commands as command lengths are
fixed.
A new command is indicated by sending 01 after the preamble. Code 01 is the start-of-frame indicator. After
the start-of-frame indicator is the 2-bit command field. Code 10 is the command code for a read. Code 01 is the
command code for a write. Codes 00 and 11 are invalid.
Immediately following the command code are 5 bits of device address. If the address matches the address
assigned to the DLKPC192S then the command is processed by the DLKPC192S; otherwise the command is
ignored, although it may be processed by another device on the MDIO interface.
Immediately following the address are 5 bits of register address. The register address specifies which of the
possible 32 registers within the DLKPC192S is to be accessed (i.e., read or written based upon the command
value). If the register address is that of a nonexistent DLKPC192S register, writes are ignored and reads are
answered with zeros.
The two bit times following the register address are used as turnaround bits. These bits times are used for read
operations, but exist even in write operations. During write operations, the sender sends a 10 sequence during
these two bit times. During read operations, the sender stops driving the data signals during the first bit time
and the addressed device starts driving a 0 during the second bit time. It should be noted that, while the data
from the processor is valid on the rising edge of MDC, data from the device is clocked onto the MDIO signal
using the rising edge. The timing of the data read during a read command has a different timing relationship
to MDC than data being transferred by the processor.
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