參數(shù)資料
型號(hào): DLKPC192S
英文描述: 10Gbps Ethernet LAN Physical Coding Sublayer (PCS) Device
中文描述: 10Gbps的以太網(wǎng)物理編碼子層(PCS)設(shè)備
文件頁數(shù): 10/25頁
文件大?。?/td> 360K
代理商: DLKPC192S
!
SLLS536
AUGUST 2002
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
XGMII receive data bus timing
The receiver portion of the XGMII interface on the DLKPC192S outputs the decoded data on RD[0:31] and byte
control flags, KF[0:3]. The XGMII interface is a DDR interface, so data is transferred on both the rising and falling
edges of the XGMII receive data clock, RC. The basic timing is shown in Figure 8. Detailed timing information
is provided later in this document.
RC
RD[0:31]
KF[0:3]
t(SETUP)
t(HOLD)
t(SETUP)
t(HOLD)
Figure 8. Receive Interface Timing
data reception latency
The data reception latency of the DLKPC192S is defined as the delay from the edge of the XSBI transmit clock
when valid data is latched on the XSBI to the rising edge of the XGMII transmit clock, RC, when the last bit of
the same data is output on the XGMII interface. The latency (R
LATENCY
) is measured in RXC clock periods. The
maximum latency is 81 RXC clock periods. If the latency is not an exact multiple of RXC clock periods, then the
latency value is rounded down to the next lower number of RXC clock periods for the minimum latency and
rounded up to the next higher integer number of RXC clock periods for the maximum latency. The standard
requires a round-trip latency of less than 224 high-speed clock cycles.
RXCP/RXCN
RXDP[0:15]
RXDN[0:15]
RC
RXD[0:31]
RG[0:3]
A
B
C
R(Latency MAX)
R(Latency MIN)
*+A
+B
B
+C
+*
Figure 9. Receive Latency
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