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參數(shù)資料
| 型號(hào)： | DK-DEV-4CGX150N |
| 廠商： | Altera |
| 文件頁(yè)數(shù)： | 33/42頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEVELOPMENT CYCLONE IV GX |
| 應(yīng)用說(shuō)明： | Cyclone IV Design Guidelines |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview |
| 軟件下載： | DK-DEV-4CGX150N Kit Install |
| 特色產(chǎn)品： | Cyclone? IV GX FPGA Development Kit |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | CYCLONE® IV GX |
| 類(lèi)型： | FPGA |
| 適用于相關(guān)產(chǎn)品： | Cyclone IV GX |
| 所含物品： | 板，線纜，文檔，電源 |
| 其它名稱(chēng)： | 544-2713 |
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Chapter 1: Cyclone IV Device Datasheet
1–39
Glossary
December 2013
Altera Corporation
R
RL
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver Input
Waveform
Receiver input waveform for LVDS and LVPECL differential standards:
Receiver input
skew margin
(RSKM)
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
S
Single-ended
voltage-
referenced I/O
Standard
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
SW (Sampling
Window)
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Table 1–46. Glossary (Part 3 of 5)
Letter
Term
Definitions
Single-Ended Waveform
Differential Waveform (Mathematical Function of Positive & Negative Channel)
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
V
ID
V
ID
0 V
V
CM
p
- n
V
ID
VIH(AC)
VIH(DC)
VREF
VIL(DC)
VIL(AC)
VOH
VOL
VCCIO
VSS
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參數(shù)描述 |
|---|---|
| DK-DEV-4CGX150N | 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX ((NS |
| DK-DEV-4S100G5N | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For EP4S100G5F RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓: |
| DK-DEV-4SE530N | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For EP4SE530H35 RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓: |
| DK-DEV-4SGX230N | 功能描述:可編程邏輯 IC 開(kāi)發(fā)工具 FPGA Development Kit For EP4SGX230KF40C2N RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類(lèi)型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類(lèi)型: 工作電源電壓: |
| DK-DEV-4SGX230N/C2 | 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件狀態(tài):過(guò)期 類(lèi)型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:EP4SGX230KF40C2N 內(nèi)容:板，線纜，電源 標(biāo)準(zhǔn)包裝:1 |
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