參數(shù)資料
型號： DK-DEV-4CGX150N
廠商： Altera
文件頁數(shù)： 27/42頁
文件大小： 0K
描述： KIT DEVELOPMENT CYCLONE IV GX
應(yīng)用說明： Cyclone IV Design Guidelines
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
Cyclone IV FPGA Family Overview
軟件下載： DK-DEV-4CGX150N Kit Install
特色產(chǎn)品： Cyclone? IV GX FPGA Development Kit
標(biāo)準(zhǔn)包裝： 1
系列： CYCLONE® IV GX
類型： FPGA
適用于相關(guān)產(chǎn)品： Cyclone IV GX
所含物品： 板，線纜，文檔，電源
其它名稱： 544-2713
Chapter 1: Cyclone IV Device Datasheet
1–33
Switching Characteristics
December 2013
Altera Corporation
f For more information about the supported maximum clock rate, device and pin
planning, IP implementation, and device termination, refer to Section III: System
Performance Specifications of the External Memory Interface Handbook.
Table 1–37 lists the memory output clock jitter specifications for Cyclone IV devices.
Duty Cycle Distortion Specifications
Table 1–38 lists the worst case duty cycle distortion for Cyclone IV devices.
OCT Calibration Timing Specification
Table 1–39 lists the duration of calibration for series OCT with calibration at device
power-up for Cyclone IV devices.
Table 1–37. Memory Output Clock Jitter Specifications for Cyclone IV Devices (1), (2)
Parameter
Symbol
Min
Max
Unit
Clock period jitter
tJIT(per)
–125
125
ps
Cycle-to-cycle period jitter
tJIT(cc)
–200
200
ps
Duty cycle jitter
tJIT(duty)
–150
150
ps
Notes to Table 1–37:
(1) Memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2
standard.
(2) The clock jitter specification applies to memory output clock pins generated using DDIO circuits clocked by a PLL
output routed on a global clock (GCLK) network.
Table 1–38. Duty Cycle Distortion on Cyclone IV Devices I/O Pins (1), (2), (3)
Symbol
C6
C7, I7
C8, I8L, A7
C9L
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output Duty Cycle
4555
%
Notes to Table 1–38:
(1) The duty cycle distortion specification applies to clock outputs from the PLLs, global clock tree, and IOE driving the dedicated and general
purpose I/O pins.
(2) Cyclone IV devices meet the specified duty cycle distortion at the maximum output toggle rate for each combination of I/O standard and current
strength.
(3) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support
C6, C7, C8, I7, and A7 speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.
Table 1–39. Timing Specification for Series OCT with Calibration at Device Power-Up for
Cyclone IV Devices (1)
Symbol
Description
Maximum
Units
tOCTCAL
Duration of series OCT with
calibration at device power-up
20
s
Note to Table 1–39:
(1) OCT calibration takes place after device configuration and before entering user mode.
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參數(shù)描述
DK-DEV-4CGX150N 制造商:Altera Corporation 功能描述:KIT STARTER CYCLONE IV GX ((NS
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DK-DEV-4SGX230N/C2 功能描述:EP4SGX230KF40C2N Stratix? IV GX FPGA Evaluation Board 制造商:altera 系列:Stratix? IV GX 零件狀態(tài):過期 類型:FPGA 配套使用產(chǎn)品/相關(guān)產(chǎn)品:EP4SGX230KF40C2N 內(nèi)容:板，線纜，電源 標(biāo)準(zhǔn)包裝:1
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