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| 型號(hào)： | DEM-VSP2262Y |
| 英文描述： | CCD SIGNAL PROCESSOR for DIGITAL CAMERAS |
| 中文描述： | CCD信號(hào)處理器的數(shù)碼相機(jī) |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 224K |
| 代理商： | DEM-VSP2262Y |
VSP2262
SBMS011
7
THEORY OF OPERATION
INTRODUCTION
The VSP2262 is a complete mixed-signal IC that contains
all of the key features associated with the processing of the
CCD imager output signal in a video camera, a digital still
camera, security camera, or similar applications (see the
simplified block diagram on page 1 for details). The VSP2262
includes a Correlated Double Sampler (CDS), Program-
mable Gain Amplifier (PGA), Analog-to-Digital Converter
(ADC), input clamp, Optical Black (OB) level clamp loop,
serial interface, timing control, reference voltage generator,
and general-purpose 8-bit Digital-to-Analog Converters
(DAC). We recommend an off-chip emitter follower buffer
between the CCD output and the VSP2262 CCDIN input.
The PGA gain control, clock polarity setting, and operation
mode can be selected through the serial interface. All param-
eters are reset to the default value when the RESET pin goes
LOW asynchronously from the clocks.
CORRELATED DOUBLE SAMPLER (CDS)
The output signal of a CCD imager is sampled twice during
one pixel period: once at the reference interval and the other
at the data interval. Subtracting these two samples from each
other extracts the video information of the pixel as well as
removes any noise that is common, or correlated, to both the
intervals. Thus, the CDS is very important in reducing the
reset noise and low-frequency noises that are present on the
CCD output signal. Figure 1 shows the simplified block
diagram of the CDS and input clamp.
FIGURE 1. Simplified Block Diagram of CDS and Input
Clamp.
The CDS is driven through an off-chip coupling capacitor
(C
IN
). AC coupling is strongly recommended because the
DC level of the CCD output signal is usually several volts
too high for the CDS to work properly.
A 0.1
μ
F capacitor is recommended for C
IN
, depending on
the application environment. Additionally, we recommend
an off-chip emitter follower buffer that can drive more than
10pF, because the 10pF capacitor and a few pF of stray
capacitance can be seen at the input pin. The analog input
signal range at the CCDIN pin is 1Vp-p, and the appropriate
common-mode voltage for the CDS is around 0.5V to 1.5V.
The reference level is sampled during SHP active period,
and the voltage level is held on sampling capacitor C
1
at the
trailing edge of SHP. The data level is sampled during SHD
active period, and the voltage level is held on the sampling
capacitor C
2
at the trailing edge of SHD. The switched-
capacitor amplifier then performs the subtraction of these
two levels.
The user can select the active polarity of SHP/SHD (Active
HIGH or Active LOW) through the serial interface (refer to
the “Serial Interface” section for more detail). The default
value of SHP/SHD is “Active LOW”. However, immediately
after power ON, this value is Unknown. For this reason, the
appropriate value must be set by using the serial interface, or
reset to the default value by strobing the RESET pin. The
descriptions and the timing diagrams in this data sheet are all
based on the polarity of Active LOW (default value).
INPUT CLAMP OR DUMMY PIXEL CLAMP
The buffered CCD output is capacitively coupled to the
VSP2262. The purpose of the input clamp is to restore the
DC component of the input signal that was lost with the AC
coupling and establish the desired DC bias point for the
CDS. A simplified block diagram of the input clamp is
shown in Figure 1. The input level is clamped to the internal
reference voltage, CM (1.5V), during the dummy pixel
interval. More specifically, when both CLPDM and SHP are
active, the dummy clamp function becomes active. If the
dummy pixels and/or the CLPDM pulse are not available in
your system, the CLPOB pulse can be used in place of
CLPDM, as long as the clamping takes place during black
pixels. In this case, both the CPLDM pin (active at same
timing as CLPOB) and SHP become active during the
optical black pixel interval, and then the dummy clamp
function becomes active.
The active polarity of CLPDM and SHP (Active HIGH or
Active LOW) can be selected through the serial interface
(refer to the “Serial Interface” section for more detail).
The default value of CLPDM and SHP is “Active LOW”.
However, immediately after power ON, this value is Un-
known. For this reason, the appropriate value must be set by
using the serial interface, or reset to the default value by
strobing the RESET pin. The descriptions and the timing
diagrams in this data sheet are all based on the polarity of
Active LOW (default value).
HIGH PERFORMANCE ANALOG-TO-DIGITAL
CONVERTER (ADC)
The ADC utilizes a fully differential and pipelined architec-
ture. This ADC is well suited for low-voltage operations,
low power consumption requirements, and high-speed appli-
cations. It guarantees 12-bit resolution with no missing
codes. The VSP2262 includes a reference voltage generator
for the ADC. REFP (Positive Reference, pin 38), REFN
OPA
C
IN
C
1
10pF
C
2
10pF
CM (1.5V)
CCDIN
SHP
SHD
CCD
Output
SHP
CLPDM
VSP2262
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