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參數(shù)資料
| 型號： | DEM-VSP2262Y |
| 英文描述： | CCD SIGNAL PROCESSOR for DIGITAL CAMERAS |
| 中文描述： | CCD信號處理器的數(shù)碼相機 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 224K |
| 代理商： | DEM-VSP2262Y |
VSP2262
SBMS011
2
SPECIFICATIONS
At T
A
= +25
°
C, V
CC
= +3.0V, DRV
DD
= +3.0V, Conversion Rate (f
ADCCK
) = 20MHz, unless otherwise noted.
VSP2262Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
CONVERSION RATE
20
MHz
DIGITAL INPUT
Logic Family
Input Voltage
TTL
1.7
1.0
LOW to HIGH Threshold Voltage (VT+)
HIGH to LOW Threshold Voltage (VT
–
)
Logic HIGH (I
IH
) V
IN
= +3V
Logic LOW (I
IL
) V
IN
= 0V
V
V
μ
A
μ
A
Input Current
±
20
±
20
DIGITAL OUTPUT
Logic Family
Logic Coding
Output Voltage
CMOS
Straight Binary
Logic HIGH (V
OH
) I
OH
=
–
2mA
Logic LOW (V
OL
) I
OL
= 2mA
2.4
V
V
%
pF
V
0.4
ADCCK Clock Duty Cycle
Input Capacitance
Maximum Input Voltage
50
5
–
0.3
5.3
ANALOG INPUT
(CCDIN)
Input Signal Level for Full-Scale Out
Input Capitance
Input Limit
PGA Gain = 0dB
900
mV
pF
V
15
–
0.3
3.3
TRANSFER CHARACTERISTICS
Differential Non-Linearity (DNL)
Integral Non-Linearity (INL)
No Missing Codes
Step Response Settling Time
Overload Recovery Time
Data Latency
Signal-to-Noise Ratio
(1)
PGA Gain = 0dB
PGA Gain = 0dB
±
0.5
±
1
LSB
LSB
Guaranteed
1
2
9 (Fixed)
79
55
Full-Scale Step Input
Step Input from 1.8V to 0V
Pixel
Pixels
Clock Cycles
dB
dB
mV
Grounded Input Cap, PGA Gain = 0dB
Grounded Input Cap, Gain = +24dB
CCD Offset Correction Range
–
180
200
CDS
Reference Sample Settling Time
Data Sample Settling Time
Within 1LSB, Driver Impedance = 50
Within 1LSB, Driver Impedance = 50
11
11
ns
ns
INPUT CLAMP
Clamp-On Resistance
Clamp Level
400
1.5
V
PROGRAMMABLE GAIN AMP
(PGA)
Gain-Control Resolution
Maximum Gain
High Gain
Medium Gain
Low Gain
Minimum Gain
Gain Control Error
10
42
34
20
0
–
6
±
0.5
Bits
dB
dB
dB
dB
dB
dB
Gain Code = 1111111111
Gain Code = 1101001000
Gain Code = 1000100000
Gain Code = 0010000000
Gain Code = 0000000000
OPTICAL BLACK CLAMP LOOP
Control DAC Resolution
Optical Black Clamp Level
10
Bits
LSB
LSB
μ
A
μ
A
μ
s
V/s
Programmable Range of Clamp Level
OBCLP Level at CODE = 1000
COB Pin
COB Pin
C
COB
= 0.1
μ
F
C
COB
= 0.1
μ
F, Output Current from Control DAC is Saturated
2
60
130
±
0.15
±
153
Min Output Current for Control DAC
Max Output Current for Control DAC
Loop Time Constant
Slew Rate
1530
REFERENCE
Positive Reference Voltage
Negative Reference Voltage
1.75
1.25
V
V
Supply Voltage
Power Dissipation
V
, DRV
2.7
3.0
86
6
3.6
V
Normal Operation Mode: No Load, DAC0 and DAC1 are Suspended
Stand-By Mode: f
ADCCK
= Not Apply
mW
mW
TEMPERATURE RANGE
Operating Temperature
Thermal Resistance
–
25
+85
°
C
θ
JA
LQFP-48
100
°
C/W
NOTE: (1) SNR = 20 log(full-scale voltage/rms noise).
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