參數(shù)資料
型號(hào)： DAC757IDGSR
廠商： Texas Instruments, Inc.
英文描述： QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER
中文描述： 四，12位，低功耗，電壓輸出，I2C接口的數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù)： 24/31頁(yè)
文件大?。?/td> 783K
代理商： DAC757IDGSR
www.ti.com
Resistor
String DAC
Powerdown
Circuitry
V
OUT
Amplifier
Resistor
Network
DAC7574
SLAS375–JUNE 2003
Power-Down Modes
The DAC7574 contains four separate power-down modes of operation. The modes are programmable via two
most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits
correspond to the mode of operation of the device.
Table 8. Power-Down Modes of Operation for the DAC7574
CTRL[0]
MSB[7]
MSB[6]
OPERATING MODE
1
0
0
High Impedance Output
1 k
to GND
100 k
to GND
1
0
1
1
1
0
1
1
1
High Impedance
When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 μA at 5 V per
channel. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not
only does the supply current fall but also the output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the advantage that the output impedance of the device
is known while in power-down mode. There are three different options: The output is connected internally to GND
through a 1 k
resistor, a 100 k
resistor or left open-circuit (high impedance). The output stage is illustrated in
Figure 39.
Figure 39. Output Stage During Power Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit power down is typically 2.5 μs for V
DD
= 5 V and 5
μs for V
DD
= 3 V. (See the Typical Curves section for additional information.)
The DAC7574 offers a flexible power-down interface based on channel register operation. A channel consists of
a single 12 bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR
and DR are both 14 bits wide. Two MSBs represent the power-down condition and the 12 LSBs represent data
for TR and DR. By using bits 13 and 14 of TR and DR, a power-down condition can be temporarily stored and
used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[13] and TR[12] (DR[13]
and DR[12]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC7574 treats power-down
conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a
power-down condition to all the DAC7574s in the system, or it is possible to simultaneously power down a
channel while updating data on other channels.
CURRENT CONSUMPTION
The DAC7574 typically consumes 150μA at V
DD
= 5 V and 125μA at V
DD
= 3 V for each active channel, including
reference current consumption. Additional current consumption can occur at the digital inputs if V
IH
<< V
DD
. For
most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In
power-down mode, typical current consumption is 200 nA. A delay time of 10 to 20 ms after a power-down
command is issued to the DAC is typically sufficient for the power-down current to drop below 10 μA.
24
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