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參數(shù)資料
| 型號： | DAC757IDGSR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，12位，低功耗，電壓輸出，I2C接口的數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 14/31頁 |
| 文件大小： | 783K |
| 代理商： | DAC757IDGSR |
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Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1
2
7
8
9
ACK
1
2
3 - 8
9
ACK
Address
R/W
DAC7574
SLAS375–JUNE 2003
Figure 34. Bus Protocol
DAC7574 I
2
C Update Sequence
The DAC7574 requires a start condition, a valid I
2
C address, a control byte, an MSB byte, and an LSB byte for a
single update. After the receipt of each byte, DAC7574 acknowledges by pulling the SDA line low during the high
period of a single clock pulse. A valid I
2
C address selects the DAC7574. The control byte sets the operational
mode of the selected DAC7574. Once the operational mode is selected by the control byte, DAC7574 expects an
MSB byte followed by an LSB byte for data update to occur. DAC7574 performs an update on the falling edge of
the acknowledge signal that follows the LSB byte.
Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte
continuously determine the type of update performed. Thus, for the first update, DAC7574 requires a start
condition, a valid I
2
C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates,
DAC7574 needs an MSB byte and an LSB byte as long as the control command remains the same.
Using the I
2
C high-speed mode (f
scl
= 3.4 MHz), the clock running at 3.4 MHz, each 12-bit DAC update other than
the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge
signal), at 188.88 KSPS. Using the fast mode (f
scl
= 400 kHz), clock running at 400 kHz, maximum DAC update
rate is limited to 22.22 KSPS. Once a stop condition is received DAC7574 releases the I
2
C bus and awaits a new
start condition.
Address Byte
MSB
LSB
1
0
0
1
1
A1
A0
R/W
The address byte is the first byte received following the START condition from the master device. The first five
bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select
bits A1 and A0. The A1, A0 address inputs can be connected to V
DD
or digital GND, or can be actively driven by
TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of
the DAC7574. Up to 4 devices (DAC7574) can still be connected to the same I
2
C-Bus.
14
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