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參數(shù)資料
| 型號(hào)： | DAC757IDGSR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | QUAD, 12-BIT, LOW-POWER, VOLTAGE OUTPUT, I2C INTERFACE DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 四，12位，低功耗，電壓輸出，I2C接口的數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 23/31頁 |
| 文件大?。?/td> | 783K |
| 代理商： | DAC757IDGSR |
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DAC7574
SLAS375–JUNE 2003
Master Receiver Reading From a Slave Transmitter (DAC7574) in HS-Mode
When reading data to the DAC7574 in HS-MODE, the master begins to transmit, what is called the
HS-Master
Code
(0000 1XXX) in F/S-mode. No device is allowed to acknowledge the
HS-Master Code
, so the
HS-Master
Code
is followed by a NOT acknowledge.
The Master then
switches
to HS-mode and issues a REPEATED START condition, followed by the address byte
(with R/W = 0) after which the DAC7574 acknowledges by pulling SDA low. This address byte is usually followed
by the control byte, which is also acknowledged by the DAC7574.
Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1).
This is acknowledged by the DAC7574, indicating that it is prepared to transmit data. Two or Three bytes of data
are then read back from the DAC7574, depending on the (PD0-Bit). The value of
Buff-Sel1
and
Buff-Sel0
determines, which channel data is read back. A STOP condition follows.
With the (PD0-Bit = 0) the DAC7574 transmits 2 bytes of data,
HIGH-BYTE
followed by
LOW-BYTE
(refer to
Table 7 HS-Mode Readback Sequence).
With the (PD0-Bit = 1) the DAC7574 transmits 3 bytes of data,
POWER-DOWN-BYTE
followed by the
HIGH-BYTE
followed by the
LOW-BYTE
(refer to Table 7 HS-Mode Readback Sequence).
Table 7. Master Receiver Reading Slave Transmitter (DAC7574) in HS-Mode
HS MODE READBACK SEQUENCE
Transmitter
MSB
6
5
4
3
2
1
LSB
Comment
Master
Start
Begin sequence
Master
0
0
0
0
1
X
X
X
HS Mode Master Code
No device may acknowledge HS
master code
NONE
Not Acknowledge
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Write addressing (
R/W=0
)
DAC7574
DAC7574 Acknowledges
Master
0
0
Load 1
Load 0
X
Buff Sel 1
Buff Sel 0
PD0
Control byte (
PD0 = 1
)
DAC7574
DAC7574 Acknowledges
Master
Repeated Start
Master
1
0
0
1
1
A1
A0
R/W
Read addressing (
R/W=1
)
DAC7574
DAC7574 Acknowledges
DAC7574
PD1
PD2
1
1
1
1
1
1
Power-down byte
Master
Master Acknowledges
DAC7574
D11
D10
D9
D8
D7
D6
D5
D4
Reading data word, high byte
Master
Master Acknowledges
DAC7574
D3
D2
D1
D0
x
x
x
x
Reading data word, low byte
Master
Master Not Acknowledges
Master signal end of read
Master
Stop or Repeated Start
Done
Power-On Reset
The DAC7574 contains a power-on-reset circuit that controls the output voltage during power up. On power up,
the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC
while it is in the process of powering up. No device pin should be brought high before supply is applied.
23
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