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參數(shù)資料
| 型號： | DAC3550A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: RSZ/P - 1kVDC |
| 中文描述： | 32-BIT DAC, PQFP44 |
| 封裝： | METRIC, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 8/35頁 |
| 文件大?。?/td> | 626K |
| 代理商： | DAC3550A |
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DAC 3550A
8
Micronas
2.10. Clock System
The advantage of the DAC 3550A clock system is that
no external master clock is needed. Most DACs need
256
×
fs
audio
, 384
×
fs
audio
, or at least an asynchro-
nous clock.
All internal clocks are generated by a PLL circuit,
which locks to the I
2
S bit clock (CLI). If no I
2
S clock is
present, the PLL runs free, and it is guaranteed that
there is always a clock to keep the IC controllable by
I
2
C.
The device can be set to two different modes:
–
Standard mode
–
MPEG mode
In the standard mode, I
2
C subaddressing is possible
(ADR0, ADR1, ADR2).
MPEG mode always uses ADR3.
To select the modes, the MCS1/MCS2 pins must be
set according to Table 2
–
2.
2.10.1. Standard Mode
–
without I
2
C
In standard mode, sample rates from 48 kHz to
32 kHz are handled without I
2
C control automati-
cally. The setting for this range is the default setting.
–
with I
2
C
Sample rates below 32 kHz require an I
2
C control to
set the PLL divider. This ensures that even at low
sample rates, the DAC 3550A runs at a high clock
rate. This avoids audible effects due to the noise-
shaping technique of the DAC 3550A. Sample rate
range is continuous from 8 to 50 kHz. The I
2
C set-
ting of low sample rates must follow according to
Section 3.6.
“
Control Registers
”
on page 15.
An additional mode allows automatic sample rate
detection. In this case, the clock oscillator is
required and must run at frequencies between
13.3 MHz to 17 MHz. This mode, however, does not
support continuous sample rates. Only the following
sample rates are allowed:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, 48 kHz
The sample rate detection allows a tolerance of
±
200 ppm at WSI.
If the oscillator is not used for automatic sample rate
detection, it can be used as a general-purpose clock
for the application. The frequency range in this case is
10 MHz to 25 MHz.
2.10.2. MPEG Mode
This mode should be used in conjunction with
MAS 3507D in MPEG player applications. In this case
a 14.725 MHz signal is needed to provide a clock for
the MAS 3507D and to allow an automatic sample rate
detection in the DAC 3550A. All MPEG sample rates
from 8 to 48 kHz can be detected. The internal pro-
cessing and the DAC itself are automatically adjusted
to keep constant performance throughout the entire
range. I
2
C control for sample rate adjustment is not
needed in this case. Register SR_REG[0:2] is locked
to SRC_A; see Section 3.6.
“
Control Registers
”
on
page 15.
The MPEG sample rates:
8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz,
24 kHz, 32 kHz, 44.1 kHz, 48 kHz
As in standard mode, the sample rate detection allows
a tolerance of
±
200 ppm at WSI.
Subaddressing is not possible in MPEG mode; this
means, in multi-DAC systems, only one DAC 3550A
can run in MPEG mode.
Table 2
–
2:
Operation Modes
MCS1
MCS2
Mode
Sub-
address
Default
Sample
Rate
0
0
Stan-
dard
ADR0
32
–
48 kHz
0
1
Stan-
dard
ADR1
32
–
48 kHz
1
0
Stan-
dard
ADR2
32
–
48 kHz
1
1
MPEG
ADR3
Automatic
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