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參數(shù)資料
| 型號： | DAC3550A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | DAC |
| 英文描述： | ECONOLINE: RSZ/P - 1kVDC |
| 中文描述： | 32-BIT DAC, PQFP44 |
| 封裝： | METRIC, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 12/35頁 |
| 文件大?。?/td> | 626K |
| 代理商： | DAC3550A |
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DAC 3550A
12
Micronas
3.3. Pin Descriptions
3.3.1. Power Supply Pins
The DAC 3550A combines various analog and digital
functions which may be used in different modes. For
optimized performance, major parts have their own
power supply pins. All VSS power supply pins must be
connected.
VDD (18)
VSS (17)
The VDD and VSS power supply pair are connected
internally with all digital parts of the DAC 3550A.
AVDD0 (9)
AVSS0 (3)
AVDD0 and AVSS0 are separate power supply pins
that are exclusively used for the on-chip headphone/
loudspeaker amplifiers.
AVDD1 (10)
AVSS1 (2)
The AVDD1 and AVSS1 pins supply the analog audio
processing parts, except for the headphone/loud-
speaker amplifiers.
3.3.2. Analog Audio Pins
AGNDC (1)
Reference for analog audio signals. This pin is used as
reference for the internal op amps. This pin must be
blocked against VREF with a 3.3
μ
F capacitor.
Note:
The pin has a typical DC-level of 1.5/2.25 V. It
can be used as reference input for external op amps
when no current load is applied.
VREF (44)
Reference ground for the internal band-gap and bias-
ing circuits. This pin should be connected to a clean
ground potential. Any external distortions on this pin
will affect the analog performance of the DAC 3550A.
AUX1L (31)
AUX1R (32)
AUX2L (29)
AUX2R (30)
The AUX pins provide two analog stereo inputs. Auxil-
iary input signals, e.g. the output of a conventional
receiver circuit or the output of a tape recorder can be
connected with these inputs. The input signals have to
be connected by capacitive coupling.
FOUTL (37)
FOPL (38)
FINL (39)
FOUTR (41)
FOPR (42)
FINR (43)
Filter op amps are provided in the analog baseband
signal paths. These inverting op amps are freely
accessible for external use by these pins.
The FOUTL/R pins are connected with the buffered
output of the internal switch matrix. The FOPL/R-pins
are directly connected with the inverting inputs of the
filter op amps. The FINL/R pins are connected with the
outputs of the op amps. The driving capability of the
FOUTL/R pins is not sufficient for standard line output
signals. Only the FINL/R pins are suitable for line out-
put.
OUTL (5)
OUTR (7)
The OUTL/R pins are connected to the internal output
amplifiers. They can be used for either stereo head-
phones or a mono loudspeaker. The signal of the right
channel amplifier can be inverted for mono loud-
speaker operation.
Caution:
A short circuit at these pins for more than a
momentary period may result in destruction of the
internal circuits.
3.3.3. Oscillator and Clock Pins
XTI (12)
XTO (13)
The XTI pin is connected to the input of the internal
crystal oscillator, the XTO pin to its output. Both pins
should be directly connected to the crystal and two
ground-connected capacitors (see application dia-
gram).
CLKOUT (14)
The CLKOUT pin provides a buffered output of the
crystal oscillator.
Caution:
Power dissipation limit may be exceeded in
case of short to VSS or VDD.
CLI (23)
DAI (24)
WSI (25)
These three pins are inputs for the digital audio data
DAI, frame indication signal WSI, and bit clock CLI.
The digital audio data is transmitted in an I
2
S-compati-
ble format. Audio word lengths of 16 and 32 bits are
supported, as well as SONY and Philips I
2
S protocol.
SCL (15)
SDA (16)
SCL (serial clock) and SDA (serial data) provide the
connection to the serial control interface (I
2
C).
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