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參數(shù)資料
| 型號： | CYW305OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK W305 SOLANO 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:15 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
W305B
...................... Document #: 38-07262 Rev. *B Page 15 of 20
How to Program CPU Output Frequency
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
Fcpu = G * (N+3)/(M+3)
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 5.
The following table lists the recommended frequency output
ranges for each PLL Gear Constant and its associated Bus
Frequency Ratio so that the maximum AGP and PCI output
frequencies are less than or equal to 83.1 MHz and 41.5 MHz,
respectively.
WD_EN
0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode.
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.
Note. W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery
frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will
not respond to any attempt to change output frequency via the SMBus control bytes. System software
can unlock W305B from its recovery frequency mode by clearing the WD_EN bit.
WD_TO_STATUS
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
WD_TIMER[4:0]
These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the
pre-scaler.
The timer can support a value of 150 ms to 4.8 sec. when the pre-scaler is set to 150 ms. If the pre-scaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.
WD_PRE_SCALER
0 = 150 ms
1 = 2.5 sec
RST_EN_WD
This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
RST_EN_FC
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
Table 6. Register Summary (continued)
Name
Description
Table 7. Recommended CPU Frequency Range for Different PLL Gear Ratio
Gear Constants
Bus Frequency Ratio
(CPU/SDRAM/AGP/PCI)
Recommended Output Frequency Range (CPU/SDRAM/AGP/PCI)
Lower Limits
(N=77, M=48)
Upper Limits
(N=106, M=39)
G1 (32.00494)
66 / 100 / 66 / 33
50.2 / 75.8 / 50.2 / 25.1
83.1 / 124.7 / 83.1 / 41.5
G2 (48.00741)
100 / 100 / 66 / 33
75.3 / 75.3 / 50.2 / 25.1
124.6 / 124.6 / 83.1 / 41.5
G3 (64.00988)
133 / 133 / 66 / 33
or
133 / 100 / 66 / 33
100.4 / 100.4 / 50.2 / 25.1
or
100.4 / 75.3 / 50.2 / 25.1
166.1 / 166.1 / 83.1 / 41.5
or
166.1 / 124.5 / 83.1 / 41.5
G4 (96.01482)
200 / 200 / 66 / 33
150.6 / 150.6 / 50.2 / 25.1
249.2 / 249.2 / 83.1 / 41.5
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