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參數(shù)資料
| 型號(hào)： | CYW305OXCT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK W305 SOLANO 56SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:15 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-SSOP |
| 包裝： | 帶卷 (TR) |
W305B
........................ Document #: 38-07262 Rev. *B Page 9 of 20
Byte 6: Vendor ID & Revision ID Register (Read Only)
Bit
Name
Default
Pin Description
Bit 7
Revision_ID3
0
Revision ID bit[3]
Bit 6
Revision_ID2
0
Revision ID bit[2]
Bit 5
Revision_ID1
0
Revision ID bit[1]
Bit 4
Revision_ID0
0
Revision ID bit[0]
Bit 3
Vendor_ID3
1
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 2
Vendor_ID2
0
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 1
Vendor _ID1
0
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit 0
Vendor _ID0
0
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Byte 7: Control Register 7
Bit
Pin#
Name
Default
Pin Description
Bit 7
-
Reserved
0
Reserved
Bit 6
24
24_48MHz_DRV
1
0 = Norm, 1 = High Drive
Bit 5
23
48MHz_DRV
1
0 = Norm, 1 = High Drive
Bit 4
22
48MHz_DRV
1
0 = Norm, 1 = High Drive
Bit 3
24
24_48MHz
1
(Active/Inactive)
Bit 2
23
48 MHz
1
(Active/Inactive)
Bit 1
22
48 MHz
1
(Active/Inactive)
Bit 0
--
Reserved
0
Reserved
Byte 8: Watchdog Timer Register
Bit
Name
Default
Pin Description
Bit 7
PCI_Skew1
0
PCI skew control
00 = Normal
01 = –500ps
10 = Reserved
11 = +500ps
Bit 6
PCI_Skew0
0
Bit 5
WD_TIMER4
1
These bits store the time-out value of the Watchdog timer. The scale of the
timer is determine by the pre-scaler.
The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set
to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5
sec. to 80 sec.
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.
Bit 4
WD_TIMER3
1
Bit 3
WD_TIMER2
1
Bit 2
WD_TIMER1
1
Bit 1
WD_TIMER0
1
Bit 0
WD_PRE_SCALER
0
0 = 150 ms
1 = 2.5 sec
Byte 9: System RESET and Watchdog Timer Register
Bit
Name
Default
Pin Description
Bit 7
SDRAM_DRV
0
SDRAM clock output drive strength
0 = Normal
1 = High Drive
Bit 6
PCI_DRV
0
PCI clock output drive strength
0 = Normal
1 = High Drive
Bit 5
FS_Override
0
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
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