參數(shù)資料
型號: PI90LV387AE
廠商: Pericom
文件頁數(shù): 1/7頁
文件大?。?/td> 0K
描述: IC 16 DIFF LINE DVR HS 64-TSSOP
產(chǎn)品變化通告: Product Discontinuation 09/Dec/2010
標(biāo)準(zhǔn)包裝: 28
類型: 線路驅(qū)動器,發(fā)射器
驅(qū)動器/接收器數(shù): 16/0
規(guī)程: LVDS
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 64-TFSOP (0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 64-TSSOP
包裝: 管件
1
PS8573D
11/11/08
2DO4 –
GND
1
VCC
1DIN2
1DIN3
1DIN4
EN2
2DIN4
GND
VCC
2
VCC
3
GND
4
EN1
5
1DIN1
6
7
8
9
10
2DIN1
11
2DIN2
12
2DIN3
13
14
15
16
17
GND
18
3DIN1
19
3DIN2
20
3DIN3
21
3DIN4
22
EN3
23
4DIN1
24
64
63
62
61
60
59
58
57
56
55
2DO2+
54
2DO2–
53
2DO3+
52
51
50
49
48
47
46
45
3DO4 –
3DO4+
44
3DO3 –
3DO3+
3DO2 –
3DO2+
3DO1 –
3DO1+
2DO3 –
2DO4+
2DO1+
2DO1 –
1DO4+
1DO4 –
1DO3+
1DO3 –
1DO2+
1DO2 –
1DO1+
1DO1 –
43
42
41
25
26
27
28
29
30
31
32
40
39
37
36
35
34
33
4DIN4
EN3
GND
VCC
4DIN2
4DIN3
VCC
GND
4DO1 –
4DO4 –
4DO4+
4DO3 –
4DO3+
4DO2 –
4DO2+
4DO1+
Features
Sixteen line drivers meet or exceed the requirements of the
ANSI EIA/TIA-644 Standard
Designed for signaling rates up to 500 Mbps with very low
radiation (EMI)
Low voltage differential signaling with typical output voltage
of 350mV into :
– 100Ω load (PI90LV387)
– 50Ω load (PI90LVB387)
Propagation delay times less than 2.6ns
Output skew is less than 150ps
Part-to-part skew is less than 1.5ns
35mW total power dissipation in each driver operating at 200
MHz
Bus-pin ESD protection exceeds 10kV
Low voltage TTL (LVTTL) logic inputs are 5V tolerant
Packaging (Pb-free & Green available):
-64-Pin TSSOP (A)
Description
PI90LV387/ PI90LVB387 consists of sixteen differential line
drivers that implement the electrical characteristics of low-volt-
age differential signaling (LVDS). This signaling technique lowers
output voltage levels to reduce power, increase switching speeds,
and allow operation with a 3V supply rail.
The intended application of this device and signaling technique
is for point-to-point baseband (single termination) and multi-
point (double termination) data transmission over a controlled
impedance media of approximately 100Ω and 50Ω (LVB387).
The transmission media may be printed-circuit board traces, back-
planes, or cables. The large number of drivers integrated into the
same substrate, with the low pulse skew of balanced signaling,
allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion
16-channel receivers, the PI90LV386 or PI90LVT386, over 400
million data transfers per second in single-edge clocked systems
are possible with very little power.
(Note: The ultimate rate and distance of data transfer is dependent
upon attenuation characteristics of the media, the noise coupling
to the environment, and other system characteristics.)
The drivers are enabled in groups of ve. When disabled, driver
outputs are at a high impedance. Each driver input (DIN) and en-
able (EN) have an internal pulldown that drives the input to a low
level when open circuited.
The parts are characterized for operation from –40°C to 85°C.
PI90LV387/ PI90LVB387
High-Speed Differential Line Drivers
DO1+
DIN1
DO1–
DO2+
DO2–
DIN2
EN
DO3+
DIN3
DO3–
DO4+
DO4–
DIN4
1 of 4
Block Diagram
Pin Diagram
64-Pin
A
08-0295
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