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參數(shù)資料
| 型號： | CYW2331 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers |
| 中文描述： | 雙串行輸入鎖相環(huán)2.0千兆赫和600兆赫預(yù)分頻器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 259K |
| 代理商： | CYW2331 |
CYW2331
PRELIMINARY
6
Serial Data Input
Data is input serially using the DATA, CLOCK, and LE pins. Two control bits direct data as described in
Table 1
.
Notes:
2.
3.
4.
5.
t1–t5 = t > 0.5 μs.
CLOCK may remain HIGH after latching in data.
DATA is shifted in with the MSB first.
For DATA definitions, refer to
Table 2
.
Serial Data Input Timing Waveform
[2, 3, 4, 5]
Timing Waveforms
(continued)
CLOCK
//
LE
//
//
//
//
//
//
t2
t1
t3
t4
t5
DATA
PD = MSB
PRE
B1
A7
CNT2
CNT1 = LSB
//
t6
//
//
Table 1. Control Configuration
CNT1
0
CNT2
0
Function
Program Reference 2
: R = 3 to 32767, set PLL2 (low frequency) phase detector
polarity, set current in PLL2, set PLL2 to Hi-Impedance state, set monitor selector to PLL2.
Program Reference 1:
R = 3 to 32767, set PLL1 (high frequency) phase detector
polarity, set current in PLL1, set PLL1 to Hi-Impedance state, set monitor selector to PLL1
Program Counter for PLL2:
A = 0 to 15, B = 3 to 2047, set PLL2 prescaler ratio, set PLL2
to power-down.
Program Counter for PLL1:
A = 0 to 127, B = 3 to 2047, set PLL1 prescaler ratio, set
PLL1 to power-down.
0
1
1
0
1
1
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