- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380227 > CYW2331 (Cypress Semiconductor Corp.) Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers PDF資料下載
參數(shù)資料
| 型號(hào)： | CYW2331 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Dual Serial Input PLL with 2.0-GHz and 600-MHz Prescalers |
| 中文描述： | 雙串行輸入鎖相環(huán)2.0千兆赫和600兆赫預(yù)分頻器 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 259K |
| 代理商： | CYW2331 |
CYW2331
PRELIMINARY
2
Pin Definitions
Pin Name
V
CC
1
Pin
No.
(TSSOP)
1
Pin
No.
(CSP)
24
Pin
No.
(MLF)
19
Pin
Type
P
Pin Description
Power Supply Connection for PLL1 and PLL2:
When power
is removed from both the V
CC
1 and V
CC
2 pins, all latched data
is lost.
PLL1 Charge Pump Rail Voltage:
This voltage accommodates
VCO circuits with tuning voltages higher than the V
CC
of PLL1.
PLL1 Charge Pump Output:
The phase detector gain is I
P
/2
π
.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
Input to PLL1 Prescaler:
Maximum frequency 2.0 GHz.
Complementary Input to PLL1 Prescaler:
A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
Oscillator Input:
This input has a V
CC
/2 threshold and CMOS
logic level sensitivity.
Lock Detect Pin of PLL1 Section:
This output is HIGH when
the loop is locked. It is multiplexed to the output of the program-
mable counters or reference dividers in the test program mode.
(Refer to
Table 3
for configuration.)
Data Clock Input:
One bit of data is loaded into the Shift Reg-
ister on the rising edge of this signal.
Serial Data Input
Load Enable:
On the rising edge of this signal, the data stored
in the Shift Register is latched into the reference counter and
configuration controls, PLL1 or PLL2 depending on the state of
the control bits.
Complementary Input to PLL2 Prescaler:
A bypass capacitor
should be placed as close as possible to this pin and must be
connected directly to the ground plane.
Input to PLL2 Prescaler:
Maximum frequency 600 MHz.
PLL2 Charge Pump Output:
The phase detector gain is I
P
/2
π
.
Sense polarity can be reversed by setting the FC bit in software
(via the Shift Register).
PLL2 Charge Pump Rail Voltage:
This voltage accommodates
VCO circuits with tuning voltages higher than the V
CC
of PLL2.
Power Supply Connections for PLL1 and PLL2:
When power
is removed from both the V
CC
1 and V
CC
2 pins, all latched data
is lost.
Analog and Digital Ground Connections:
This pin must be
grounded.
V
P
1
2
2
20
P
D
O
PLL1
3
3
1
O
F
IN
1
F
IN
1#
5
6
5
6
3
4
I
I
OSC_IN
8
8
6
I
F
O
/LD
10
11
8
O
CLOCK
11
12
9
I
DATA
LE
12
13
14
15
10
11
I
I
F
IN
2#
15
17
13
I
F
IN
2
D
O
PLL2
16
18
18
20
14
16
I
O
V
P
2
19
22
17
P
V
CC
2
20
23
18
P
GND
4, 7, 9,
14, 17
4, 7,
10,
16, 19
1, 9,
13, 21
2, 5, 7,
12, 15
G
N/C
N/A
N/A
N/C
No Connect
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYW2336 | Dual Serial Input PLL with 2.0- and 1.1-GHz Prescalers(帶2.0-GHz 預(yù)標(biāo)定器的串聯(lián)輸入PLL) |
| CYW256OXC | Multiconductor Paired Security UTP Cable; Number of Conductors:8; Conductor Size AWG:23; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:4; Impedance:100ohm; Jacket Color:Gray RoHS Compliant: Yes |
| CYW256OXCT | Multiconductor Paired Security UTP Cable; Number of Conductors:8; Conductor Size AWG:23; No. Strands x Strand Size:Solid; Jacket Material:Polyvinylchloride (PVC); Number of Pairs:4; Impedance:100ohm; Jacket Color:Black RoHS Compliant: Yes |
| CYW3335 | Dual Serial Input PLL with 2.5-GHz Prescalers(帶2.5-GHz 預(yù)標(biāo)定器的串聯(lián)輸入PLL) |
| CYWM6934 | WirelessUSB LS Radio Module |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYW2338 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual Serial Input PLL with 2.5- and 1.1-GHz Prescalers |
| CYW2338ZI | 制造商:Cypress Semiconductor 功能描述: |
| CYW2338ZIT | 制造商:Cypress Semiconductor 功能描述: |
| CYW255OXC | 功能描述:時(shí)鐘緩沖器 200MhZ-24 Out Buff 4 DDR3 SDRAM DIMMS RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYW255OXCT | 功能描述:時(shí)鐘緩沖器 200MhZ-24 Out Buff 4 DDR3 SDRAM DIMMS RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。