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參數(shù)資料
| 型號(hào)： | CYW15G0403DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, BGA-256 |
| 文件頁數(shù)： | 45/45頁 |
| 文件大小： | 517K |
| 代理商： | CYW15G0403DXB-BGI |
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CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 45 of 45
Document History Page
Document Title: CYP(V)(W)15G0403DXB Independent Clock Quad HOTLink II Transceiver
Document Number: 38-02065
ISSUE
DATE
CHANGE
**
118422
09/24/02
LNM
*A
125289
04/04/03
CGX
REV.
ECN NO.
ORIG. OF
DESCRIPTION OF CHANGE
New Data Sheet
Revised entire data sheet
Redefined device
Provided AC timing information for TXERRx
Added additional information regarding the availability of half-rate
RXCLKx± when REFCLKx is a full-rate clock with RXCKSELx = 1
Added influence of ULCx input on LFIx status
Added influence of DECMODEx on decoder bypass
Revised the text for “Device Configuration and Control Interface” for
better clarity
Removed the timing parameter t
RREFDV
and added the timing
parameter t
RREFDW
instead. This change was done to provide a more
meaningful timing parameter
Revised t
RREFDA
from 9.5 ns to 9.7 ns
Added additional information to “Device Configuration Strategy”
Removed dependence of DECMODEx on decoder bypass.
Revised AC timing parameters (AC Electrical Characteristics) to
match final device characterization.
Expanded the CDR Range Controller’s permissible frequency offset
between incoming serial signalling rate and Reference clock from
±200-PPM to ±1500-PPM (changed parameter t
REFRX
).
Added CYW15G0403DXB part number for OBSAI RP3 compliance
to support operating data rate up to 1540 MBaud. Made changes to
reflect OBSAI RP3 and CPR compliance. Added Pb-Free Package
option for all parts listed in the data sheet.
Modified Timing Parameters
Changed MBd to MBaud in SPDSEL pin description
Revised setup and hold time parameters (t
TXDH
, t
TREFDS
, t
TREFDH
,
t
RXDv–
, t
RXDv+
,
t
RXDV+
,
t
REFxDV–
, t
REFxDV+
)
Added clarification for the necessity of JTAG controller reset and the
methods to implement it.
*B
128692
08/14/03
PDS
*C
234390
See ECN
PDS
*D
338721
See ECN
SUA
*E
384307
See ECN
AGT
*F
1034001
See ECN
UKK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYW15G0403DXB-BGXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYW15G0403DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYW15GO403DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYW170-01SXC | 功能描述:時(shí)鐘緩沖器 133MHz Clock RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYW170-01SXCT | 功能描述:時(shí)鐘緩沖器 133MHz Clock RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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