- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379101 > CYW15G0403DXB-BGI (CYPRESS SEMICONDUCTOR CORP) Independent Clock Quad HOTLink II⑩ Transceiver PDF資料下載
參數(shù)資料
| 型號： | CYW15G0403DXB-BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, BGA-256 |
| 文件頁數(shù)： | 11/45頁 |
| 文件大?。?/td> | 517K |
| 代理商： | CYW15G0403DXB-BGI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當(dāng)前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
CYP15G0403DXB
CYV15G0403DXB
CYW15G0403DXB
Document #: 38-02065 Rev. *F
Page 11 of 45
LFIA
LFIB
LFIC
LFID
LVTTL Output,
asynchronous
Link Fault Indication Output
. LFIx is an output status indicator signal. LFIx is the
logical OR of six internal conditions. LFIx is asserted LOW when any of the following
conditions is true:
Received serial data rate outside expected range
Analog amplitude below expected levels
Transition density lower than expected
Receive channel disabled
ULCx is LOW
Absence of REFCLKx±.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
Control Write Enable
. The WREN input writes the values of the DATA[7:0] bus into
the latch specified by the address location on the ADDR[3:0] bus.
[5]
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
Control Addressing Bus
. The ADDR[3:0] bus is the input address bus used to
configure the device. The WREN input writes the values of the DATA[7:0] bus into the
latch specified by the address location on the ADDR[3:0] bus.
[5]
Table 9 on page 20
lists the configuration latches within the device, and the initialization value of the
latches upon the assertion of RESET.
Table 10 on page 24
shows how the latches
are mapped in the device.
DATA[7:0]
LVTTL input
asynchronous,
internal pull-up
Control Data Bus
. The DATA[7:0] bus is the input data bus used to configure the
device. The WREN input writes the values of the DATA[7:0] bus into the latch
specified by address location on the ADDR[3:0] bus.
[5 ]
Table 9
lists the configuration
latches within the device, and the initialization value of the latches upon the assertion
of RESET.
Table 10
shows how the latches are mapped in the device.
Internal Device Configuration Latches
RFMODE[A..D][1:0] Internal Latch
[6]
FRAMCHAR[A..D] Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
SDASEL[A..D][1:0] Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Internal Latch
[6]
Reframe Mode Select
.
Framing Character Select
.
DECMODE[A..D]
Receiver Decoder Mode Select
.
DECBYP[A..D]
Receiver Decoder Bypass
.
RXCKSEL[A..D]
Receive Clock Select
.
RXRATE[A..D]
Receive Clock Rate Select
.
Signal Detect Amplitude Select
.
ENCBYP[A..D]
Transmit Encoder Bypassed
.
TXCKSEL[A..D]
Transmit Clock Select
.
TXRATE[A..D]
Transmit PLL Clock Rate Select
.
RFEN[A..D]
Reframe Enable
.
RXPLLPD[A..D]
Receive Channel Power Control
.
RXBIST[A..D]
Receive Bist Disabled
.
TXBIST[A..D]
Transmit Bist Disabled
.
OE2[A..D]
Differential Serial Output Driver 2 Enable
.
OE1[A..D]
Differential Serial Output Driver 1 Enable
.
Notes
5. See
“Device Configuration and Control Interface” on page 20
for detailed information on the operation of the Configuration Interface.
6. See
“Device Configuration and Control Interface” on page 20
for detailed information on the internal latches.
Pin Descriptions
(continued)
CYP(V)(W)15G0403DXB Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYT2506 | White LED Step-Up Converter |
| CYV15G0104 | Independent Clock HOTLink II?? Serializer and Reclocking Deserializer |
| CYV15G0104TRB-BGC | Independent Clock HOTLink II?? Serializer and Reclocking Deserializer |
| CYV15G0403TB | Independent Clock Quad HOTLink II⑩ Serializer |
| CYV15G0403TB-BGC | Independent Clock Quad HOTLink II⑩ Serializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYW15G0403DXB-BGXC | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYW15G0403DXB-BGXI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYW15GO403DXB-BGI | 制造商:Cypress Semiconductor 功能描述: |
| CYW170-01SXC | 功能描述:時鐘緩沖器 133MHz Clock RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| CYW170-01SXCT | 功能描述:時鐘緩沖器 133MHz Clock RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。