參數(shù)資料
型號(hào)： CYW15G0401DXB
廠商： Cypress Semiconductor Corp.
英文描述： Quad HOTLink II Transceiver(四熱連接II收發(fā)器)
中文描述： 四HOTLink II收發(fā)器（四熱連接二收發(fā)器）
文件頁數(shù)： 8/53頁
文件大?。?/td> 575K
代理商： CYW15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
CYP15G0401DXB
Document #: 38-02002 Rev. *L
Page 8 of 53
Pin Descriptions
CYP(V)(W)15G0401DXB
Quad HOTLink II Transceiver
Pin Name
I/O Characteristics
Signal Description
Transmit Path Data Signals
TXPERA
TXPERB
TXPERC
TXPERD
LVTTL Output, changes
relative to REFCLK
↑
[4]
Transmit Path Parity Error
. Active HIGH. Asserted (HIGH) if parity checking is
enabled and a parity error is detected at the Encoder. This output is HIGH for one
transmit character clock period to indicate detection of a parity error in the character
presented to the Encoder.
If a parity error is detected, the character in error is replaced with a C0.7 character to
force a corresponding bad-character detection at the remote end of the link. This
replacement takes place regardless of the encoded/non-encoded state of the
interface.
When BIST is enabled for the specific transmit channel, BIST progress is presented
on these outputs. Once every 511 character times (plus a 16-character Word Sync
Sequence when the receive channels are clocked by a common clock, i.e., RXCKSEL
= LOW or HIGH), the associated TXPERx signal will pulse HIGH for one
transmit-character clock period (if RXCKSEL= MID) or seventeen transmit- character
clock periods (if RXCKSEL = LOW or HIGH and Encoder is enabled) to indicate a
complete pass through the BIST sequence. Therefore, in this case TXPERx signal
will pulse HIGH for one transmit-character clock period.
These outputs also provide indication of a transmit Phase-align Buffer underflow or
overflow. When the transmit Phase-align Buffers are enabled (TXCKSEL
≠
LOW, or
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is
detected, TXPERx for the channel in error is asserted and remains asserted until
either an atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to
re-center the transmit Phase-align Buffers.
TXCTA[1:0]
TXCTB[1:0]
TXCTC[1:0]
TXCTD[1:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx
↑
or
REFCLK
↑
[4]
Transmit Control
. These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL, and are passed to the Encoder or Transmit
Shifter. They identify how the associated TXDx[7:0] characters are interpreted. When
the Encoder is bypassed, these inputs are interpreted as data bits of 10-bit input
character. When the Encoder is enabled, these inputs determine if the TXDx[7:0]
character is encoded as Data, a Special Character code, a K28.5 fill character or a
Word Sync Sequence. See
Table 1
for details.
TXDA[7:0]
TXDB[7:0]
TXDC[7:0]
TXDD[7:0]
LVTTL Input,
synchronous,
sampled by the
selected TXCLKx
↑
or
REFCLK
↑
[4]
Transmit Data Inputs
. These inputs are captured on the rising edge of the transmit
interface clock as selected by TXCKSEL and passed to the Encoder or Transmit
Shifter.
When the Encoder is enabled (TXMODE[1:0]
≠
LOW), TXDx[7:0] specify the specific
data or command character to be sent. When the Encoder is bypassed, these inputs
are interpreted as data bits of the 10-bit input character. See
Table 1
for details.
Transmit Path Odd Parity
. When parity checking is enabled (PARCTL
≠
LOW), the
parity captured at these inputs is XORed with the data on the associated TXDx bus
(and sometimes TXCT[1:0]) to verify the integrity of the captured character. See
Table 2
for details.
TXOPA
TXOPB
TXOPC
TXOPD
LVTTL Input,
synchronous,
internal pull-up,
sampled by the
respective TXCLKx
↑
or
REFCLK
↑
[4]
SCSEL
LVTTL Input,
synchronous,
internal pull-down,
sampled by
TXCLKA
↑
or REFCLK
↑
[4]
Special Character Select
. Used in some transmit modes along with TXCTx[1:0] to
encode special characters or to initiate a Word Sync Sequence. When the transmit
paths are configured for independent input clocks (TXCKSEL = MID), SCSEL is
captured relative to TXCLKA
↑
.
Note:
4.
When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling
edges of REFCLK.
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