參數(shù)資料
型號： CYW15G0401DXB
廠商： Cypress Semiconductor Corp.
英文描述： Quad HOTLink II Transceiver(四熱連接II收發(fā)器)
中文描述： 四HOTLink II收發(fā)器（四熱連接二收發(fā)器）
文件頁數(shù)： 37/53頁
文件大?。?/td> 575K
代理商： CYW15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
CYP15G0401DXB
Document #: 38-02002 Rev. *L
Page 37 of 53
t
TXCLKR[32, 33, 34]
t
TXCLKF[32, 33, 34]
t
TXDS
t
TXDH
f
TOS
t
TXCLKO
t
TXCLKOD+
t
TXCLKOD–
CYP(V)(W)15G0401DXB
Receiver LVTTL Switching Characteristics
Over the Operating Range
f
RS
RXCLKx Clock Output Frequency
t
RXCLKP
RXCLKx Period
t
RXCLKH
RXCLKx HIGH Time (RXRATE = LOW)
RXCLKx HIGH Time (RXRATE = HIGH)
t
RXCLKL
RXCLKx LOW Time (RXRATE = LOW)
RXCLKx LOW Time (RXRATE = HIGH)
t
RXCLKD
RXCLKx Duty Cycle centered at 50%
t
RXCLKR [32]
RXCLKx Rise Time
t
RXCLKF [32]
RXCLKx Fall Time
t
RXDV– [35]
Status and Data Valid Time to RXCLKx (RXCKSEL HIGH or MID)
Status and Data Valid Time to RXCLKx
(HALF RATE RECOVERED
CLOCK)
t
RXDV+ [35]
Status and Data Valid Time From RXCLKx
(RXCKSEL HIGH or MID)
Status and Data Valid Time From RXCLKx
(HALF RATE RECOVERED
CLOCK)
TXCLKx Rise Time
TXCLKx Fall Time
Transmit Data Set-Up Time to
TXCLKx
↑
(TXCKSEL
≠
LOW)
Transmit Data Hold Time from TXCLKx
↑
(TXCKSEL
≠
LOW)
TXCLKO Clock Frequency = 1x or 2x REFCLK Frequency
TXCLKO Period
TXCLKO+ Duty Cycle with 60% HIGH time
TXCLKO– Duty Cycle with 40% HIGH time
0.2
0.2
1.7
0.8
20
1.7
1.7
ns
ns
ns
ns
MHz
ns
ns
ns
150
[30]
50
+0.5
+1.0
6.66
[31]
–1.0
–0.5
9.75
6.66
[31]
2.33
[32]
5.66
2.33
[32]
5.66
–1.0
0.3
0.3
5UI – 1.5
5UI – 1.0
150
[30]
102.56
26.64
52.28
26.64
52.28
+1.0
1.2
1.2
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5UI – 1.8
5UI – 2.3
ns
ns
CYP(V)(W)15G0401DXB
REFCLK Switching Characteristics
Over the Operating Range
f
REF
REFCLK Clock Frequency
t
REFCLK
REFCLK Period
t
REFH
REFCLK HIGH Time (TXRATE = HIGH)
REFCLK HIGH Time (TXRATE = LOW)
t
REFL
REFCLK LOW Time (TXRATE = HIGH)
REFCLK LOW Time (TXRATE = LOW)
t
REFD [36]
REFCLK Duty Cycle
t
REFR [32, 33, 34]
REFCLK Rise Time (20% – 80%)
t
REFF [32, 33, 34]
REFCLK Fall Time (20% – 80%)
t
TREFDS
Transmit Data Setup Time to
REFCLK (TXCKSEL
=
LOW)
t
TREFDH
Transmit Data Hold Time from REFCLK
(TXCKSEL
=
LOW)
t
RREFDA[37]
Receive Data Access Time from REFCLK (RXCKSEL
=
LOW)
t
RREFDV
Receive Data Valid Time from REFCLK
(RXCKSEL
=
LOW)
Notes:
33. The ratio of rise time to falling time must not vary by greater than 2:1.
34. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
35. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
36. The duty cycle specification is a simultaneous condition with the t
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLK duty cycle
cannot be as large as 30% – 70%.
37. Since this timing parameter is greater than the minimum time period of REFCLK it sets an upper limit to the frequency in which REFCLKx can be used to clock
the receive data out of the output register. For predictable timing, users can use this parameter only if REFCLK period is greater than sum of t
and
set-up time of the upstream device. When this condition is not true, RXCLKC± or RXCLKA± (a buffered or delayed version of REFCLK when RXCKSELx =
LOW) could be used to clock the receive data out of the device.
19.5
6.66
[31]
5.9
2.9
[32]
5.9
2.9
[32]
30
150
[30]
51.28
MHz
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
ns
70
2
2
1.7
0.8
9.5
2.5
CYP(V)(W)15G0401DXB
AC Characteristics
Over the Operating Range (continued)
Parameter
Description
Min.
Max.
Unit
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