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參數(shù)資料
| 型號： | CYV15G0403TB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Serializer |
| 中文描述： | 獨(dú)立時(shí)鐘四的HOTLink二⑩串行 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大小： | 324K |
| 代理商： | CYV15G0403TB |
CYV15G0403TB
Document #: 38-02104 Rev. *C
Page 8 of 21
SPDSELA
SPDSELB
SPDSELC
SPDSELD
3-Level Select
[4]
static control input
Serial Rate Select
. The SPDSELx inputs specify the operating signaling-rate range of
each channel’s PLL.
LOW = 195–400 MBd
MID = 400–800 MBd
HIGH = 800–1500 MBd.
Device Configuration and Control Bus Signals
WREN
LVTTL input,
asynchronous,
internal pull-up
ADDR[3:0]
LVTTL input
asynchronous,
internal pull-up
by the address location on the ADDR[3:0] bus.
[5]
Table 2 on page 11
lists the configuration
latches within the device, and the initialization value of the latches upon the assertion of
RESET.
Table 3 on page 12
shows how the latches are mapped in the device.
DATA[4:0]
LVTTL input
asynchronous,
internal pull-up
location on the ADDR[3:0] bus.
[5 ]
Table 2 on page 11
lists the configuration latches within
the device, and the initialization value of the latches upon the assertion of RESET.
Table 3
on page 12
shows how the latches are mapped in the device.
Internal Device Configuration Latches
TXCKSEL[A..D] Internal Latch
[6]
Transmit Clock Select
.
TXRATE[A..D]
Internal Latch
[6]
Transmit PLL Clock Rate Select
.
TXBIST[A..D]
Internal Latch
[6]
Transmit Bist Disabled
.
OE2[A..D]
Internal Latch
[6]
Differential Serial Output Driver 2 Enable
.
OE1[A..D]
Internal Latch
[6]
Differential Serial Output Driver 1 Enable
.
PABRST[A..D]
Internal Latch
[6]
Transmit Clock Phase Alignment Buffer Reset
.
GLEN[11..0]
Internal Latch
[6]
Global Latch Enable
.
FGLEN[2..0]
Internal Latch
[6]
Force Global Latch Enable
.
Factory Test Modes
SCANEN2
LVTTL input,
internal pull-down
CONNECT, or GND only.
TMEN3
LVTTL input,
internal pull-down
CONNECT, or GND only.
Analog I/O
OUTA1±
OUTB1±
OUTC1±
OUTD1±
tions.
OUTA2±
OUTB2±
OUTC2±
OUTD2±
Control Write Enable
. The WREN input writes the values of the DATA[4:0] bus into the
latch specified by the address location on the ADDR[3:0] bus.
[5]
Control Addressing Bus
. The ADDR[3:0] bus is the input address bus used to configure
the device. The WREN input writes the values of the DATA[4:0] bus into the latch specified
Control Data Bus
. The DATA[4:0] bus is the input data bus used to configure the device.
The WREN input writes the values of the DATA[4:0] bus into the latch specified by address
Factory Test 2.
SCANEN2 input is for factory testing only. This input may be left as a NO
Factory Test 3
. TMEN3 input is for factory testing only. This input may be left as a NO
CML Differential
Output
Primary Differential Serial Data Output
. The OUTx1± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connec-
CML Differential
Output
Secondary Differential Serial Data Output
. The OUTx2± PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic
transmitter modules, and must be AC-coupled for PECL-compatible connections.
Notes
4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually
implemented by direct connection to V
(ground). The HIGH level is usually implemented by direct connection to V
CC
(power). The MID level is usually
implemented by not connecting the input (left floating), which allows it to self bias to the proper level.
5. See
“Device Configuration and Control Interface” on page 10
for detailed information on the operation of the Configuration Interface.
6. See
“Device Configuration and Control Interface” on page 10
for detailed information on the internal latches.
Pin Definitions
(continued)
CYV15G0403TB Quad HOTLink II Serializer
Name
I/O Characteristics Signal Description
[+] Feedback
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