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參數(shù)資料
| 型號： | CYV15G0403TB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Serializer |
| 中文描述： | 獨立時鐘四的HOTLink二⑩串行 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 324K |
| 代理商： | CYV15G0403TB |
CYV15G0403TB
Document #: 38-02104 Rev. *C
Page 10 of 21
allowable range of REFCLKx± frequencies are listed in
Table 1
.
Table 1. Operating Speed Settings
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50
Ω
transmission lines. These drivers accept data from the
Transmit Shifter, which shifts the data out LSB first. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note
. When a disabled channel (i.e., both outputs disabled) is
re-enabled:
data on the serial outputs may not meet all timing specifi-
cations for up to 250
μ
s
the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
Device Configuration and Control Interface
The CYV15G0403TB is highly configurable via the configu-
ration interface. This interface allows the device to be
configured globally or allows each channel to be configured
independently.
Table 2 on page 11
lists the configuration
latches within the device including the initialization value of the
latches upon the assertion of RESET.
Table 3 on page 12
shows how the latches are mapped in the device. Each row in
the
Table 3
maps to a 5-bit latch bank. There are 16 such
write-only latch banks. When WREN = 0, the logic value in
DATA[4:0] is latched to the latch bank specified by the values
in ADDR[3:0]. The second column of
Table 3
specifies the
channels associated with the corresponding latch bank. For
example, the first three latch banks (0,1 and 2) consist of
configuration bits for channel A. The latch banks 12, 13 and 14
consist of Global configuration bits and the last latch bank (15)
is the Mask latch bank that can be configured to perform
bit-by-bit configuration.
Global Enable Function
The global enable function, controlled by the GLENx bits, is a
feature that can be used to reduce the number of write opera-
tions needed to setup the latch banks. This function is
beneficial in systems that use a common configuration in
multiple channels. The GLENx bit is present in bit 0 of latch
banks 0 through 11 only. Its default value (1) enables the global
update of the latch bank's contents. Setting the GLENx bit to
0 disables this functionality.
Latch Banks 12, 13, and 14 are used to load values in the
related latch banks in a global manner. A write operation to
latch bank 12 could do a global write to latch banks 0, 3, 6, and
9 depending on the value of GLENx in these latch banks; latch
bank 13 could do a global write to latch banks 1, 4, 7 and 10;
and latch banks 14 could do a global write to latch banks 2, 5,
8 and 11. The GLENx bit cannot be modified by a global write
operation.
Force Global Enable Function
FGLENx forces the global update of the target latch banks, but
does not change the contents of the GLENx bits. If FGLENx =
1 for the associated global channel, FGLENx forces the global
update of the target latch banks.
Mask Function
An additional latch bank (15) is used as a global mask vector
to control the update of the configuration latch banks on a
bit-by-bit basis. A logic 1 in a bit location allows for the update
of that same location of the target latch bank(s), whereas a
logic 0 disables it. The reset value of this latch bank is FFh,
thereby making its use optional by default. The mask latch
bank is not maskable. The FGLEN functionality is not affected
by the bit 0 value of the mask latch bank.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
SPDSELx
TXRATEx
REFCLKx±
Frequency
(MHz)
reserved
19.5–40
20–40
40–80
40–75
80–150
Signaling
Rate (Mbps)
LOW
1
0
1
0
1
0
195–400
MID (Open)
400–800
HIGH
800–1500
[+] Feedback
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CYV15G0403TB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Serializer |
| CYV15G0403TB-BGC | 功能描述:電信線路管理 IC 4x Indep Serializer COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0403TB-BGXC | 功能描述:電信線路管理 IC 4x Indep Serializer COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0404DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
| CYV15G0404DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver with Reclocker |
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