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參數(shù)資料
| 型號： | CYV15G0403TB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Quad HOTLink II⑩ Serializer |
| 中文描述： | 獨立時鐘四的HOTLink二⑩串行 |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 324K |
| 代理商： | CYV15G0403TB |
CYV15G0403TB
Document #: 38-02104 Rev. *C
Page 12 of 21
Device Configuration Strategy
The following is a series of ordered events needed to load the
configuration latches on a per channel basis:
1. Pulse RESET Low after device power-up. This operation
resets all four channels. Initialize the JTAG state machine
to its reset state as detailed in the
JTAG Support
section.
2. Set the static latch banks for the target channel. May be
performed using a global operation, if the application
permits it.
3. Set the dynamic bank of latches for the target channel.
Enable the output drivers. May be performed using a global
operation, if the application permits it. [Required step.]
4. Reset the Phase Alignment Buffer for the target channel.
May be performed using a global operation, if the appli-
cation permits it. [Optional if phase align buffer is
bypassed.]
JTAG Support
The CYV15G0403TB contains a JTAG port to allow system
level diagnosis of device interconnect. Of the available JTAG
modes, boundary scan, and bypass are supported. This
capability is present only on the LVTTL inputs and outputs and
the REFCLKx± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain. To ensure valid
device operation after power-up (including non-JTAG
operation), the JTAG state machine should also be initialized
to a reset state. This should be done in addition to the device
reset (using RESET). The JTAG state machine can be
initialized using TRST (asserting it LOW and deasserting it or
leaving it asserted), or by asserting TMS HIGH for at least 5
consecutive TCLK cycles. This is necessary in order to ensure
that the JTAG controller does not enter any of the test modes
after device power-up. In this JTAG reset state, the rest of the
device will be in normal operation.
Note: The order of device reset (using RESET) and JTAG
initialization does not matter.
3-Level Select Inputs
Each 3-Level select inputs reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11 respectively
JTAG ID
The JTAG device ID for the CYV15G0403TB is ‘0C810069’x.
Table 3. Device Control Latch Configuration Table
ADDR
Channel
Type
DATA4
DATA3
DATA2
DATA1
DATA0
Reset
Value
0
(0000b)
A
S
X
X
0
X
GLEN0
11111
1
(0001b)
A
S
X
0
TXCKSELA
TXRATEA
GLEN1
01101
2
(0010b)
A
D
TXBISTA
OE2A
OE1A
PABRSTA
GLEN2
10011
3
(0011b)
B
S
X
X
0
X
GLEN3
11111
4
(0100b)
B
S
X
0
TXCKSELB
TXRATEB
GLEN4
01101
5
(0101b)
B
D
TXBISTB
OE2B
OE1B
PABRSTB
GLEN5
10011
6
(0110b)
C
S
X
X
0
X
GLEN6
11111
7
(0111b)
C
S
X
0
TXCKSELC
TXRATEC
GLEN7
01101
8
(1000b)
C
D
TXBISTC
OE2C
OE1C
PABRSTC
GLEN8
10011
9
(1001b)
D
S
X
X
0
X
GLEN9
11111
10
(1010b)
D
S
X
0
TXCKSELD
TXRATED
GLEN10
01101
11
(1011b)
D
D
TXBISTD
OE2D
OE1D
PABRSTD
GLEN11
10011
12
(1100b)
GLOBAL
S
X
X
0
X
FGLEN0
N/A
13
(1101b)
GLOBAL
S
X
0
TXCKSELGL
TXRATEGL
FGLEN1
N/A
14
(1110b)
GLOBAL
D
TXBISTGL
OE2GL
OE1GL
PABRSTGL
FGLEN2
N/A
15
(1111b)
MASK
D
D4
D3
D2
D1
D0
11111
[+] Feedback
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