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參數(shù)資料
| 型號： | CYV15G0203TB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Independent Clock Dual HOTLink II Serializer |
| 中文描述： | 獨立的時鐘第二串行雙的HOTLink |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 525K |
| 代理商： | CYV15G0203TB |
PRELIMINARY
CYV15G0203TB
Document #: 38-02105 Rev. **
Page 9 of 19
associated channel. The serial signaling-rate and allowable
range of REFCLKx± frequencies are listed in
Table 1
.
The REFCLKx± inputs are differential inputs with each input
internally biased to 1.4V. If the REFCLKx+ input is connected
to a TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point. When driven by a single-ended TTL, LVTTL,
or LVCMOS clock source, connect the clock source to either
the true or complement REFCLKx input, and leave the
alternate REFCLKx input open (floating).
When both the REFCLKx+ and REFCLKx– inputs are
connected, the clock source must be a differential clock. This
can either be a differential LVPECL clock that is DC-or
AC-coupled or a differential LVTTL or LVCMOS clock.
By connecting the REFCLKx– input to an external voltage
source, it is possible to adjust the reference point of the
REFCLKx+ input for alternate logic levels. When doing so, it
is necessary to ensure that the input differential crossing point
remains within the parametric range supported by the input.
Serial Output Drivers
The serial output interface drivers use differential Current
Mode Logic (CML) drivers to provide source-matched drivers
for 50
transmission lines. These drivers accept data from the
Transmit Shifter, which shifts the data out LSB first. These
drivers have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
Transmit Channels Enabled
Each driver can be enabled or disabled separately via the
device configuration interface.
When a driver is disabled via the configuration interface, it is
internally powered down to reduce device power. If both serial
drivers for a channel are in this disabled state, the associated
internal logic for that channel is also powered down. A device
reset (RESET sampled LOW) disables all output drivers.
Note
. When a disabled channel (i.e., both outputs disabled) is
re-enabled:
data on the serial outputs may not meet all timing specifi-
cations for up to 250
μ
s
the state of the phase-align buffer cannot be guaranteed,
and a phase-align reset is required if the phase-align buffer
is used
Device Configuration and Control Interface
The CYV15G0203TB is highly configurable via the configu-
ration interface. The configuration interface allows each
channel to be configured independently.
Table 2
lists the
configuration latches within the device including the initial-
ization value of the latches upon the assertion of RESET.
Table 3
shows how the latches are mapped in the device.
Each row in the
Table 3
maps to a 4-bit latch bank. There are
6 such write-only latch banks. When WREN = 0, the logic value
in the DATA[3:0] is latched to the latch bank specified by the
values in ADDR[2:0]. The second column of
Table 3
specifies
the channels associated with the corresponding latch bank.
For example, the first three latch banks (0,1 and 2) consist of
configuration bits for channel A.
Latch Types
There are two types of latch banks: static (S) and dynamic (D).
Each channel is configured by 2 static and 1 dynamic latch
banks. The S type contain those settings that normally do not
change for a given application, whereas the D type controls
the settings that could change during the application's lifetime.
The first and second rows of each channel (address numbers
0, 1, 5, and 6) are the static control latches. The third row of
latches for each channel (address numbers 2 and 7) are the
dynamic control latches. Address numbers 3 and 4 are internal
test registers.
Static Latch Values
There are some latches in the table that have a static value
(i.e. 1, 0, or X). The latches that have a ‘1’ or ‘0’ must be
configured with their corresponding value each time that their
associated latch bank is configured. The latches that have an
‘X’ are don’t cares and can be configured with any value.
Table 1. Operating Speed Settings
SPDSELx
LOW
TXRATEx
1
0
1
0
1
0
REFCLKx±
Frequency
(MHz)
reserved
19.5 – 40
20 – 40
40 – 80
40 – 75
80 – 150
Signaling
Rate (Mbps)
195 – 400
MID (Open)
400 – 800
HIGH
800 – 1500
Table 2. Device Configuration and Control Latch Descriptions
Name
TXCKSELA
TXCKSELB
Signal Description
Transmit Clock Select
. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock
source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input
register TXDx[9:0] is clocked by REFCLKx
↑.
In this mode, the phase alignment buffer is bypassed. When
TXCKSELx = 0, the associated TXCLKx
↑
is used to clock in the input register TXDx[9:0].
Transmit PLL Clock Rate Select
. The initialization value of the TXRATEx latch = 0. TXRATEx is used
to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the
associated REFCLKx± input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the
TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated
REFCLKx± input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx± input
by 20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice
the frequency rate of the REFCLKx± input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data
Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx
= LOW, is an invalid state and this combination is reserved.
TXRATEA
TXRATEB
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| CYV15G0203TB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Dual HOTLink II⑩ Serializer |
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