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參數(shù)資料
| 型號(hào)： | CYV15G0101DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Single-channel HOTLink Transceiver |
| 中文描述： | 單通道的HOTLink收發(fā)器 |
| 文件頁數(shù)： | 5/39頁 |
| 文件大小： | 457K |
| 代理商： | CYV15G0101DXB |
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CYP15G0101DXB
CYV15G0101DXB
Document #: 38-02031 Rev. *I
Page 5 of 39
Pin Descriptions
CYP(V)15G0101DXB Single-channel HOTLink II
Pin Name
Transmit Path Data Signals
TXPER
LVTTL Output,
changes relative to
REFCLK
I/O Characteristics Signal Description
[3]
Transmit Path Parity Error
.
Active HIGH. Asserted (HIGH) if parity checking is enabled
(PARCTL
LOW) and a parity error is detected at the Encoder. This output is HIGH for one
transmit character-clock period to indicate detection of a parity error in the character
presented to the Encoder.
If a parity error is detected, the character in error is replaced with a C0.7 character to force
a corresponding bad-character detection at the remote end of the link. This replacement
takes place regardless of the encoded/un-encoded state of the interface.
When BIST is enabled for the specific transmit channel, BIST progress is presented on this
output. Once every 511 character times (plus a 16-character Word Sync Sequence when
the receive channel is clocked by REFCLK, i.e., RXCKSEL = LOW), the TXPER signal
pulses HIGH for one transmit-character clock period (if RXCKSEL = MID) or seventeen
transmit-character clock periods (if RXCKSEL = LOW or HIGH) to indicate a complete pass
through the BIST sequence. For RXCKSEL = LOW or HIGH, If TXMODE[1:0] = LL, then no
Word Sync Sequence is sent in BIST, and TXPER pulses HIGH for one transmit-character
clock period.
This output also provides an indication of a Phase-Align Buffer underflow/overflow condition.
When the Phase-Align Buffer is enabled (TXCKSEL
TXRATE = HIGH), and an underflow/overflow condition is detected, TXPER is asserted and
remains asserted until either an atomic Word Sync Sequence is transmitted or TXRST is
sampled LOW to recenter the Phase-Align Buffer.
Transmit Control
. These inputs are captured on the rising edge of the transmit interface
clock as selected by TXCKSEL, and are passed to the Encoder or Transmit Shifter. They
identify how the TXD[7:0] characters are interpreted. When the Encoder is enabled, these
inputs determine if the TXD[7:0] character is encoded as Data, a Special Character code,
a K28.5 fill character or a Word Sync Sequence. When the Encoder is bypassed, these
inputs are interpreted as data bits. See
Table 1
for details.
Transmit Data Inputs
. These inputs are captured on the rising edge of the transmit interface
clock as selected by TXCKSEL, and passed to the Encoder or Transmit Shifter.
LOW, or TXCKSEL = LOW and
TXCT[1:0]
LVTTL Input,
synchronous,
sampled by TXCLK
or REFCLK
[3]
TXD[7:0]
LVTTL Input,
synchronous,
sampled by TXCLK
or REFCLK
[3]
When the Encoder is enabled (TXMODE[1]
command character to be sent. When the Encoder is bypassed, these inputs are interpreted
as data bits of the 10-bit input character. See
Table 1
for details.
Transmit Path Odd Parity
. When parity checking is enabled (PARCTL
captured at this input is XORed with the data on the TXD bus (and sometimes TXCT[1:0])
to verify the integrity of the captured character. See
Table 2
for details.
LOW), TXD[7:0] specify the specific data or
TXOP
LVTTL Input,
synchronous,
internal pull-up,
sampled by TXCLK
or REFCLK
LVTTL Input,
synchronous,
internal pull-down,
sampled by TXCLK
or REFCLK
[3]
LOW), the parity
SCSEL
[3]
Special Character Select
. Used in some transmit modes along with TXCTx[1:0] to encode
special characters or to initiate a Word Sync Sequence. When the transmit path is configured
to select TXCLK to clock the input register (TXCKSEL = MID or HIGH), SCSEL is captured
relative to TXCLK .
Note:
3.
When REFCLK is configured for half-rate operation (TXRATE
=
HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges
of REFCLK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CYV15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0101DXB-BBI | 功能描述:電信線路管理 IC Single Ch Video IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0101DXB-BBXC | 功能描述:電信線路管理 IC Single Ch Video COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0101DXB-BBXI | 功能描述:電信線路管理 IC Single Ch Video IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYV15G0101DX-VIDEO | 功能描述:時(shí)鐘緩沖器 Sngl-Ch HOTLink II Transceiver RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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