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參數(shù)資料
| 型號(hào)： | CYS25G0101DX-ATI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET OC-48 Transceiver |
| 中文描述： | TRANSCEIVER, PQFP120 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-120 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 224K |
| 代理商： | CYS25G0101DX-ATI |
CYS25G0101DX
Document #: 38-02009 Rev. *J
Page 5 of 15
CYS25G0101DX Operation
The CYS25G0101DX is a highly configurable device designed
to support reliable transfer of large quantities of data using
high-speed serial links. It performs necessary clock and data
recovery, clock generation, serial-to-parallel conversion, and
parallel-to-serial conversion. CYS25G0101DX also provides
various loopback functions.
CYS25G0101DX Transmit Data Path
Operating Modes
The transmit path of the CYS25G0101DX supports 16-bit
-wide data paths.
Phase-Align Buffer
Data from the input register is passed to a phase-align buffer
(FIFO). This buffer is used to absorb clock phase differences
between the transmit input clock and the internal character
clock.
Initialization of the phase-align buffer takes place when the
FIFO_RST input is asserted LOW. When FIFO_RST is
returned HIGH, the present input clock phase relative to
TXCLKO is set. Once set, the input clock is allowed to skew in
time up to half a character period in either direction relative to
REFCLK (i.e., ±180
°)
. This time shift allows the delay path of
the character clock (relative to REFLCK) to change due to
operating voltage and temperature while not effecting the
desired operation. FIFO_RST is an asynchronous input.
FIFO_ERR is the transmit FIFO Error indicator. When HIGH,
Note:
4.
V
DDQ
equals V
CC
if interfacing to a parallel LVPECL interface.
the transmit FIFO has either under or overflowed. The FIFO
can be externally reset to clear the error indication or if no
action is taken, the internal clearing mechanism will clear the
FIFO in nine clock cycles. When the FIFO is being reset, the
output data is 1010.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a 155.52-MHz
external clock at the REFCLK input, and multiplies that clock
by 16 to generate a bit-rate clock for use by the transmit shifter.
The operating serial signaling rate and allowable range of
REFCLK frequencies is listed in
Table 7
. The REFCLK phase
noise limits to meet SONET compliancy are illustrated in
Figure 5
. The REFCLK± input is a standard LVPECL input.
Serializer
The parallel data from the phase-align buffer is passed to the
Serializer which converts the parallel data to serial data using
the bit-rate clock generated by the Transmit PLL clock multi-
plier. TXD[15] is the most significant bit of the output word, and
is transmitted first on the serial interface.
Serial Output Driver
The serial interface Output Driver makes use of high-perfor-
mance differential Current Mode Logic (CML) to provide a
source-matched driver for the transmission lines. This driver
receives its data from the Transmit Shifters or the receive
loopback data. The outputs have signal swings equivalent to
that of standard LVPECL drivers, and are capable of driving
AC-coupled optical modules or transmission lines.
LINELOOP
LVTTL input
Line Loopback Control
. When HIGH, received serial data is looped back from receive to
transmit after being reclocked by a recovered clock. When LINELOOP is LOW, the data
passed to the OUT± line driver is controlled by LOOPA. When both LINELOOP and LOOPA
are LOW, the data passed to the OUT± line driver is generated in the transmit shifter.
Analog Line Loopback
. When LINELOOP is LOW and LOOPA is HIGH, received serial
data is looped back from receive input buffer to transmit output buffer, but is not routed
through the clock and data recovery PLL. When LOOPA is LOW, the data passed to the
OUT± line driver is controlled by LINELOOP.
Loop Time Mode
. When HIGH, the extracted receive bit-clock replaces transmit bit-clock.
When LOW, the REFCLK input is multiplied by 16 to generate the transmit bit clock.
LOOPA
LVTTL input
LOOPTIME
LVTTL input
Serial I/O
OUT±
Differential CML
output
Differential CML
input
Differential Serial Data Output
. This differential CML output (+3.3V referenced) is capable
of driving terminated 50
transmission lines or commercial fiber-optic transmitter modules.
Differential Serial Data Input
. This differential input accept the serial data stream for
deserialization and clock extraction.
IN±
Power
V
CCN
V
SSN
V
CCQ
V
SSQ
V
DDQ
Power
Ground
Power
Ground
Power
+3.3V supply (for digital and low-speed I/O functions)
Signal and power ground (for digital and low-speed I/O functions)
+3.3V quiet power (for analog functions)
Quiet ground (for analog functions)
+1.5V supply for HSTL outputs
[4]
CYS25G0101DX OC-48 SONET Transceiver
(continued)
Pin Name
I/O Characteristics
Signal Description
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYS25G0101DX-ATXC | 功能描述:電信線路管理 IC BELLCORE SONET SDH OC 48 SERDES COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYS25G0101DX-ATXI | 功能描述:電信線路管理 IC BELLCORE SONET SDH OC 48 SERDES IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYS25G01K100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Physical Layer Devices |
| CYS25G01K100V1A-MGC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CYS25G01K100V1-MGC | 制造商:Cypress Semiconductor 功能描述: |
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