參數(shù)資料
型號(hào)： CYP15G0401DXA-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Quad HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256
文件頁(yè)數(shù)： 9/48頁(yè)
文件大?。?/td> 1115K
代理商： CYP15G0401DXA-BGC
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 9 of 48
Transmit Path Mode Control
TXMODE[1:0]
3-Level Select
[2]
Static Control inputs
Transmit Operating Mode. These inputs are interpreted to select one of nine operating
modes of the transmit path. See
Table 3
for a list of operating modes.
Receive Path Data Signals
RXDA[7:0]
RXDB[7:0]
RXDC[7:0]
RXDD[7:0]
LVTTL Output,
synchronous to the
selected RXCLKx
↑
output or
REFCLK
↑
[1]
input
LVTTL Output,
synchronous to the
selected RXCLKx
↑
output or
REFCLK
↑
[1]
input
3-state, LVTTL
Output, synchronous
to the selected
RXCLKx
↑
output or
REFCLK
↑
[1]
input
LVTTL Input
Static Control Input,
internal pull-down
Parallel Data Output. These outputs change following the rising edge of the selected
receive interface clock.
RXSTA[2:0]
RXSTB[2:0]
RXSTC[2:0]
RXSTD[2:0]
Parallel Status Output. These outputs change following the rising edge of the selected
receive interface clock. When the decoder is bypassed, RXSTx[1:0] become the two
low-order bits of the 10-bit received character, while RXSTx[2] = HIGH indicates the
presence of a COMMA character in the output register.
RXOPA
RXOPB
RXOPC
RXOPD
Receive Path Odd Parity. When parity generation is enabled (PARCTL
≠
LOW), the
parity output at these pins is valid for the data on the associated RXDx bus bits. When
parity generation is disabled (PARCTL = LOW) these output drivers are disabled
(High-Z).
RXRATE
Receive Clock Rate Select.
When LOW, the RXCLKx
±
recovered clock outputs are complementary clocks operating
at the recovered character rate. Data for the associated receive channels should be
latched on the rising edge of RXCLKx+ or falling edge of RXCLKx
–
.
When HIGH, the RXCLKx
±
recovered clock outputs are complementary clocks operat-
ing at half the character rate. Data for the associated receive channels should be latched
alternately on the rising edge of RXCLKx+ and RXCLKx
–
.
When operated with REFCLK clocking of the received parallel data outputs
(RXCKSEL = LOW), the RXRATE input is not interpreted.
Receive Path Clock and Clock Control
RXCLKA
±
RXCLKB
±
RXCLKC
±
RXCLKD
±
are output continuously at either the dual-character rate (1/20
th
the serial bit-rate) or
character rate (1/10
th
the serial bit-rate) of the data being received, as selected by
RXRATE.
When configured such that all output data paths are clocked by REFCLK instead of a
recovered clock (RXCKSEL = LOW), the RXCLKA
±
and RXCLKC
±
output drivers
present a buffered form of REFCLK, and RXCLKB+ and RXCLKD+ are static control
inputs used to select the master channel for bonding and status control. RXCLKA
±
and
RXCLKC
±
are buffered forms of REFCLK that are slightly different in phase. This phase
difference allows the user to select the optimal setup/hold timing for their specific inter-
face.
When dual-channel bonding is enabled and a recovered clock is used to present data
(RXCKSEL = HIGH), RXCLKA
±
drives the recovered clock from either receive channel
A or receive channel B as selected by RXCLKB+, and RXCLKC
±
drives the recovered
clock from either receive channel C or receive channel D as selected by RXCLKD+.
When quad-channel bonding is enabled and a recovered clock is used to present data
(RXCKSEL = HIGH), RXCLKA
±
and RXCLKC
±
output the recovered clock from receive
channel A, B, C, or D, as selected by RXCLKB+ and RXCLKD+.
RFEN
LVTTL input,
asynchronous,
internal pull-down
3-state, LVTTL
Output clock or
Static control input
Receive Character clock output or clock select input. When the receive Elasticity Buffers
are disabled (RXCKSEL = MID), these true and complement clocks are the Receive
interface clocks which are used to control timing of data output transfers. These clocks
Reframe Enable for all channels. Active HIGH. When HIGH the framers in all four chan-
nels are enabled to frame per the presently enabled framing mode.
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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CYP15G0401DXB-BGC 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0401DXB-BGI 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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