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參數(shù)資料
| 型號： | CYP15G0401DXA-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 18/48頁 |
| 文件大?。?/td> | 1115K |
| 代理商： | CYP15G0401DXA-BGC |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 18 of 48
ruptible) operation. Once it has been successfully started, it
cannot be stopped until all 16 characters have been generat-
ed. The content of the associated input register(s) is ignored
for the duration of this 16-character sequence. At the end of
this sequence, if the TXCTx[1:0] = 11 condition is sampled
again, the sequence restarts and remains uninterruptible for
the following 15 character clocks.
If parity checking is enabled, the character used to start the
Word Sync Sequence must also have correct ODD parity. This
is true even though the contents of the TXDx[7:0] bits do not
directly control the generation of characters during the Word
Sync Sequence. Once the sequence is started, parity is not
checked on the following 15 characters in the Word Sync Se-
quence.
When TXMODE[1] = H (TX modes 6, 7, and 8), the generation
of the Word Sync Sequence becomes an interruptible opera-
tion. In TX Mode 6, this sequence is started as soon as the
TXCTx[1:0] = 11 condition is detected on a channel. In order
for the sequence to continue on that channel, the TXCTx[1:0]
inputs must be sampled as 00 for the remaining 15 characters
of the sequence.
If at any time a sample period exists where TXCTx[1:0]
≠
00,
the Word Sync Sequence is terminated, and a character rep-
resenting the associated data and control bits is generated by
the Encoder. This resets the Word Sync Sequence state ma-
chine such that it will start at the beginning of the sequence at
the next occurrence of TXCTx[1:0] = 11.
When parity checking is enabled and TXMODE[1] = H, all
characters (including those in the middle of a Word Sync Se-
quence) must have correct parity. The detection of a character
with incorrect parity during a Word Sync Sequence (regard-
less of the state of TXCTx[1:0]) will interrupt that sequence
and force generation of a C0.7 SVS character. Any interruption
of the Word Sync Sequence causes the sequence to termi-
nate.
When TXCKSEL = L, the input registers for all four transmit
channels are clocked by REFCLK
[1]
. When TXCKSEL = H,
the input registers for all four transmit channels are clocked
with TXCLKA
↑
. In these clock modes all four sets of
TXCTx[1:0] inputs operate synchronous to the SCSEL input.
NOTE
: When operated in any configuration where receive
channels are bonded together, TXCKSEL must be either
LOW or HIGH (nor MID) to ensure that associated charac-
ters are transmitted in the same character cycle.
TX Mode 4
—
Atomic Word Sync and SCSEL Control of
Word Sync Sequence Generation
When configured in TX Mode 4, the SCSEL input is captured
along with the associated TXCTx[1:0] data control inputs.
These bits combine to control the interpretation of the
TXDx[7:0] bits and the characters generated by them. These
bits are interpreted as listed in
Table 6
.
When TXCKSEL = M, all transmit channels operate indepen-
dently. The SCSEL input is sampled only by TXCKA
↑
. When
the character accepted in the Channel-A Input Register has
passed any selected validation and is ready to be passed to
the Encoder, the level captured on SCSEL is passed to the
encoders of the remaining channels during this same cycle.
To avoid the possible ambiguities that may arise due to the
uncontrolled arrival of SCSEL relative to the characters in the
alternate channels, SCSEL is often used as a static configura-
tion input.
TX Mode 4 also supports an Atomic Word Sync Sequence.
Unlike TX Mode 3, this sequence is started when both SCSEL
and TXCTx[0] are sampled HIGH. With the exception of the
combination of control bits used to initiate the sequence, the
generation and operation of this Word Sync Sequence is the
same as that documented for TX Mode 3.
TX Mode 5
—
Atomic Word Sync, No SCSEL
When configured in TX Mode 5, the SCSEL signal is not used.
In addition to the standard character encodings, both with and
without atomic Word Sync Sequence generation, two addition-
al encoding mappings are controlled by the Channel Bonding
selection made through the RXMODE[1:0] inputs.
For non-bonded operation, the TXCTx[1:0] inputs for each
channel control the characters generated by that channel. The
specific characters generated by these bits are listed in
Table 7
.
TX Mode 5 also has the capability of generating an Atomic
Word Sync Sequence. For the sequence to be started, the
TXCTx[1:0] inputs must both be sampled HIGH. With the ex-
ception of the combination of control bits used to initiate the
sequence, the generation and operation of this Word Sync Se-
quence is the same as that documented for TX Mode 3.
Two additional encoding maps are provided for use when re-
ceive channel bonding is enabled. When dual-channel bond-
ing is enabled (RXMODE[1] = M), the CYP15G0401DXA is
configured such that channels A and B are bonded together to
form a two-character-wide path, and channels C and D are
bonded together to form a second two-character-wide path.
When operated in this two-channel bonded mode, the
TXCTA[0] and TXCTB[0] inputs control the interpretation of the
data on both the A and B channels, while the TXCTC[0] and
TXCTD[0] inputs control the interpretation of the data on both
the C and D channels. The characters on each half of these
bonded channels are controlled by the associated TXCTx[1]
Table 6. TX Modes 4 and 7 Encoding
S
T
T
0
1
1
1
Characters Generated
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
X
0
0
1
X
0
1
X
Table 7. TX Modes 5 and 8 Encoding, Non-Bonded
S
T
T
0
1
0
1
Characters Generated
Encoded data character
K28.5 fill character
Special character code
16-character Word Sync Sequence
X
X
X
X
0
0
1
1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0401DXA-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver |
| CYP15G0401DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver |
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| CYP15G0401DXB-BGC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DXB-BGI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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