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參數(shù)資料
| 型號(hào)： | CYP15G0401DXA-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Quad HOTLink II Transceiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 1115K |
| 代理商： | CYP15G0401DXA-BGC |
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CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 19 of 48
bit. The specific characters generated by these control bit com-
binations are listed in
Table 8
.
Note especially that any time TXCTB[0] is sampled HIGH, both
channels A and B start generating an Atomic Word Sync Se-
quence, regardless of the state of any of the other bits in the
A or B input registers (with the exception of any enabled parity
checking). In a similar fashion, anytime TXCTD[0] is sampled
HIGH, both the C and D channels start generation of an Atom-
ic Word Sync Sequence.
When RXMODE[1] = H, the CYP15G0401DXA is configured
for quad-channel bonding, such that channels A, B, C, and D
are bonded together to form a four-character-wide path. When
operated in this mode, the TXCTA[0] and TXCTB[0] inputs
control the interpretation of the data on all four channels. The
characters generated on these bonded channels are con-
trolled by the associated TXCTx[1] bit. The specific characters
generated by these bits are listed in
Table 9
.
Unlike dual-channel modes, when all four channels are bond-
ed together, the TXCTC[0] and TXCTD[0] inputs are not inter-
preted.
Transmit BIST
The transmitter interfaces contain internal pattern generators
that can be used to validate both device and link operation.
These generators are enabled by the associated BOE[x] sig-
nals listed in
Table 10
(when the BISTLE latch enable input is
HIGH). When enabled, a register in the associated transmit
channel becomes a signature pattern generator by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit viola-
tion symbols. This provides a predictable yet pseudo-random
sequence that can be matched to an identical LFSR in the
attached Receiver(s).
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator in the associated transmit
channel (or the BIST checker in the associated receive chan-
nel). When BISTLE returns LOW, the values of all BOE[x] sig-
nals are captured in the BIST Enable Latch. These values re-
main in the BIST Enable Latch until BISTLE is returned high
to open the latch again. All captured signals in the BIST Enable
Latch are set HIGH (i.e., BIST is disabled) following a a device
reset (TRSTZ is sampled LOW).
All data and data-control information present at the associated
TXDx[7:0] and TXCTx[1:0] inputs are ignored when BIST is
active on that channel. If the receive channels are configured
for common clock operation (RXCKSEL
≠
MID) each pass is
preceded by a 16-character Word Sync Sequence to allow
Elasticity Buffer alignment and management of clock-frequen-
cy variations.
Serial Output Drivers
The serial interface Output Drivers make use of high-perfor-
mance differential CML (Current Mode Logic) to provide a
source-matched driver for the transmission lines. These driv-
ers accept data from the Transmit Shifters. These outputs
have signal swings equivalent to that of standard PECL driv-
ers, and are capable of driving AC-coupled optical modules or
AC-coupled transmission lines.
Table 8. TX Modes 5 and 8, Dual-Channel Bonded
S
T
T
T
T
T
T
T
T
Characters Generated
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
Encoded data character on channel A
K28.5 fill character on channel A
Special character code on channel A
16-character word sync on channel A
Encoded data character on channel B
K28.5 fill character on channel B
Special character code on channel B
16-character word sync on channel B
16-character word sync on channels A and B
Encoded data character on channel C
K28.5 fill character on channel C
Special character code on channel C
16-character word sync on channel C
Encoded data character on channel D
K28.5 fill character on channel D
Special character code on channel D
16-character word sync on channel D
16-character word sync on channels C and D
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0401DXA-BGI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver |
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| CYP15G0401DXB-BGC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0401DXB-BGI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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