參數(shù)資料
型號(hào)： CYP15G0401DXA-BGC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Quad HOTLink II Transceiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 27 X 27 MM, 1.52 MM HEIGHT, THERMALLY ENHANCED, BGA-256
文件頁(yè)數(shù)： 10/48頁(yè)
文件大?。?/td> 1115K
代理商： CYP15G0401DXA-BGC
CYP15G0401DXA
PRELIMINARY
Document #: 38-02002 Rev. *B
Page 10 of 48
RXMODE[1:0]
3-Level Select
[2]
Static Control Inputs
3-Level Select
[2]
Static Control Input
Receive Operating Mode. These inputs are interpreted to select one of nine operating
modes of the receive path. See
Table 15
for details.
Receive Clock Mode. Selects the receive clock-source used to transfer data to the
output registers.
When LOW, all four output registers are clocked by REFCLK. RXCLKB
±
and RXCLKD
±
outputs are disabled (High-Z), and RXCLKA
±
and RXCLKC
±
present buffered and de-
layed forms of REFCLK. This clocking mode is required for channel bonding across
multiple devices.
When MID, each RXCLKx
±
output follows the recovered clock for the respective chan-
nel, as selected by RXRATE.
When HIGH, and channel bonding is enabled in dual-channel mode (RX modes 3 and
5), RXCLKA
±
outputs the recovered clock from either receive channel A or receive
channel B as selected by RXCLKB+, and RXCLKC
±
outputs the recovered clock from
either receive channel C or receive channel D as selected by RXCLKD+. These output
clocks may operate at the character-rate or half the character-rate as selected by
RXRATE.
When HIGH and channel bonding is enabled in quad channel mode (RX modes 6 and
8), or if the receive channels are operated in independent mode (RX modes 0 and 2),
RXCLKA
±
and RXCLKC
±
output the recovered clock from receive channel A, B, C, or
D, as selected by RXCLKB+ and RXCLKD+. This output clock may operate at the char-
acter-rate or half the character-rate as selected by RXRATE.
Framing Character Select. Used to control the character or portion of a character used
for character framing of the received data streams.
When LOW, the framer looks for an 8-bit positive COMMA character in the data stream.
When MID, the framer looks for both positive and negative disparity versions of the 8-
bit COMMA character.
When HIGH, the framer looks for both positive and negative disparity versions of the
K28.5 character.
Reframe Mode Select. Used to control the type of character framing used to adjust the
character boundaries (based on detection of one or more framing characters in the data
stream). This signal operates in conjunction with the presently enabled channel bonding
mode, and the type of framing character selected.
When LOW, the low-latency framer is selected. This will frame on each occurrence of
the selected framing character(s) in the received data stream. This mode of framing
stretches the recovered clock for one or multiple cycles to align that clock with the
recovered data.
When MID, the Cypress-mode multi-byte parallel framer is selected. This requires a pair
of the selected framing character(s), on identical 10-bit boundaries, within a span of 50
bits, before the character boundaries are adjusted. The recovered character clock re-
mains in the same phasing regardless of character offset.
When HIGH, the alternate mode multi-byte parallel framer is selected. This requires
detection of the selected framing character(s) of the allowed disparities in the received
data stream, on identical 10-bit boundaries, on four directly adjacent characters. The
recovered character clock remains in the same phasing regardless of character offset.
Decoder Mode Select. This input selects the behavior of the decoder block.
When LOW, the decoder is bypassed and raw 10-bit characters are passed to the output
register.
When MID, the Cypress decoder table for Special Code characters is used.
When HIGH, the alternate decoder table for Special Code characters is used.
See
Table 25
for a list of the Special Codes supported in both encoded modes.
RXCKSEL
FRAMCHAR
3-Level Select
[2]
Static Control Input
RFMODE
3-Level Select
[2]
Static Control Input
DECMODE
3-Level Select
[2]
Static Control Input
Pin Descriptions
CYP15G0401DXA Quad HOTLink II Transceiver
Name
I/O Characteristics
Signal Description
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CYP15G0401DXA-BGI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Quad HOTLink II Transceiver
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CYP15G0401DXB-BGC 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
CYP15G0401DXB-BGI 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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