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參數(shù)資料
| 型號(hào)： | CYP15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PLENUM VGA VIDEO CABLE 100 FT -MM |
| 中文描述： | 雙通道HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大?。?/td> | 577K |
| 代理商： | CYP15G0201DXB |
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CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 17 of 46
The clock multiplier PLL can accept a REFCLK input between
10 MHz and 150 MHz, however, this clock range is limited by
the operating mode of the CYP(V)15G0201DXB clock multi-
plier (controlled by TXRATE) and by the level on the SPDSEL
input.
SPDSEL is a 3-level select
[5]
(ternary) input that selects one
of three operating ranges for the serial data outputs and inputs.
The operating serial signaling-rate and allowable range of
REFCLK frequencies are listed in
.
When TXRATE = HIGH (Half-rate REFCLK), TXCKSEL =
HIGH or MID (TXCLKx or TXCLKA selected to clock input
register) is an invalid mode of operation.
The REFCLK
±
input is a differential input with each input inter-
nally biased to 1.4V. If the REFCLK+ input is connected to a
TTL, LVTTL, or LVCMOS clock source, the input signal is
recognized when it passes through the internally biased
reference point.
When both the REFCLK+ and REFCLK– inputs are
connected, the clock source must be a differential clock. This
can be either a differential LVPECL clock that is DC-or
AC-coupled, or a differential LVTTL or LVCMOS clock.
By connecting the REFCLK– input to an external voltage
source or resistive voltage divider, it is possible to adjust the
reference point of the REFCLK+ input for alternate logic levels.
When doing so it is necessary to ensure that the 0V-differential
crossing point remains within the parametric range supported
by the input.
CYP(V)15G0201DXB Receive Data Path
Serial Line Receivers
Two differential Line Receivers, INx1±
and INx2±, are
available on each channel for accepting serial data streams.
The active Serial Line Receiver on a channel is selected using
the associated INSELx input. The Serial Line Receiver inputs
are differential, and can accommodate wire interconnect and
filtering losses or transmission line attenuation greater than
16 dB. For normal operation, these inputs should receive a
signal of at least VI
DIFF
> 100 mV, or 200 mV peak-to-peak
differential. Each Line Receiver can be DC- or AC-coupled to
+3.3V powered fiber-optic interface modules (any ECL/PECL
logic family, not limited to 100K PECL) or AC-coupled to +5V
powered optical modules. The common-mode tolerance of
these line receivers accommodates a wide range of signal
termination voltages. Each receiver provides internal
DC-restoration, to the center of the receiver’s common mode
range, for AC-coupled signals.
The local loopback input (LPEN) allows the serial transmit data
outputs to be routed internally back to the Clock and Data
Recovery circuit associated with each channel. When
configured for local loopback, all transmit serial driver outputs
are forced to output a differential logic-1. This prevents local
diagnostic patterns from being broadcast to attached remote
receivers.
Signal Detect/Link Fault
Each selected Line Receiver (i.e., that routed to the Clock and
Data Recovery PLL) is simultaneously monitored for
analog amplitude above limit specified by SDASEL
transition density greater than specified limit
range controller reports the received data stream within
normal frequency range (±1500 ppm)
[12]
receive channel enabled
All of these conditions must be valid for the Signal Detect block
to indicate a valid signal is present. This status is presented on
the LFIx (Link Fault Indicator) output associated with each
receive channel, which changes synchronous to the selected
receive interface clock.
Analog Amplitude
While the majority of these signal monitors are based on fixed
constants, the analog amplitude level detection is adjustable
to allow operation with highly attenuated signals, or in
high-noise environments. This adjustment is made through the
SDASEL signal, a 3-level select
[5]
input, which sets the trip
point for the detection of a valid signal at one of three levels,
as listed in
Table 11
. This control input effects the analog
monitors for all receive channels.
The Analog Signal Detect monitors are active for the Line
Receiver, selected by the associated INSELx input. When
configured for local loopback (LPEN = HIGH), no line
receivers are selected, and the LFIx output for each channel
reports only the receive VCO frequency out-of-range and
transition density status of the associated transmit signal.
When local loopback is active, the Analog Signal Detect
Monitors are disabled.
Notes:
12. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK
must be within ±1500 PPM (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates
the frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the limits
specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet
compliant, the frequency stability of the crystal needs to be within ±100PPM
13. The peak amplitudes listed in this table are for typical waveforms that have generally 3 – 4 transitions for every ten bits. In a worse case environment the signals
may have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
Table 10. Operating Speed Settings
SPDSEL
LOW
TXRATE
1
0
1
0
1
0
REFCLK
Frequency
(MHz)
Reserved
19.5–40
20–40
40–80
40–75
80–150
Signaling
Rate (MBaud)
195–400
MID (Open)
400–800
HIGH
800–1500
Table 11. Analog Amplitude Detect Valid Signal Levels
[13]
SDASEL
LOW
MID (Open)
HIGH
Typical signal with peak amplitudes above
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0201DXB-BBC | ULTRA-THIN SVGA CABLE 10FT MALE/MALE |
| CYP15G0201DXB-BBI | ULTRA-THIN SVGA CABLE 15FT MALE/MALE |
| CYV15G0201DXB | Dual-channel HOTLink II Transceiver |
| CYV15G0201DXB-BBC | Dual-channel HOTLink II Transceiver |
| CYV15G0404RB-BGC | Independent Clock Quad HOTLink Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0201DXB_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYP15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBXI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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