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參數(shù)資料
| 型號： | CYP15G0201DXB |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | PLENUM VGA VIDEO CABLE 100 FT -MM |
| 中文描述： | 雙通道HOTLink II收發(fā)器 |
| 文件頁數(shù)： | 16/46頁 |
| 文件大小： | 577K |
| 代理商： | CYP15G0201DXB |
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CYP15G0201DXB
CYV15G0201DXB
Document #: 38-02058 Rev. *G
Page 16 of 46
Note especially that any time TXCTB[0] is sampled HIGH, both
channels A and B start generating an Atomic Word Sync
Sequence, regardless of the state of any of the other bits in the
A or B Input Registers (with the exception of any enabled parity
checking).
Transmit BIST
Each transmit channel contains an internal pattern generator
that can be used to validate both device and link operation.
These generators are enabled by the associated BOE[x]
signals listed in
Table 9
(when the BISTLE latch enable input
is HIGH). When enabled, a register in the associated transmit
channel becomes a signature pattern generator by logically
converting to a Linear Feedback Shift Register (LFSR). This
LFSR generates a 511-character sequence that includes all
Data and Special Character codes, including the explicit
violation symbols. This provides a predictable yet
pseudo-random sequence that can be matched to an identical
LFSR in the attached Receiver(s). If the receive channels are
configured for common clock operation (RXCKSEL
≠
MID)
and Encoder is enabled (TXMODE[1]
≠
LOW) each pass is
preceded by a 16-character Word Sync Sequence to allow
Elasticity Buffer alignment and management of clock-
frequency variations.
When the BISTLE signal is HIGH, any BOE[x] input that is
LOW enables the BIST generator in the associated transmit
channel (or the BIST checker in the associated receive
channel). When BISTLE returns LOW, the values of all BOE[x]
signals are captured in the BIST Enable Latch. These values
remain in the BIST Enable Latch until BISTLE is returned
HIGH to open the latch. A device reset, (TRSTZ sampled
LOW) presets the BIST Enable Latch to disable BIST on all
channels. All data and data-control information present at the
associated TXDx[7:0] and TXCTx[1:0] inputs are ignored
when BIST is active on that channel.
Serial Output Drivers
The serial interface Output Drivers use high-performance
differential CML (Current Mode Logic) to provide a
source-matched driver for the transmission lines. These
drivers accept data from the Transmit Shifters. These outputs
have signal swings equivalent to that of standard PECL
drivers, and are capable of driving AC-coupled optical
modules or transmission lines.
When configured for local loopback (LPEN = HIGH), all
enabled Serial Drivers are configured to drive a static
differential logic-1.
Each Serial Driver can be enabled or disabled separately
through the BOE[3:0] inputs, as controlled by the OELE
latch-enable signal. When OELE is HIGH, the signals present
on the BOE[3:0] inputs are passed through the Serial Output
Enable Latch to control the serial output drivers. The BOE[3:0]
input associated with a specific OUTxy
±
driver is listed in
Table 9
.
Table 9. Output Enable, BIST, and Receive Channel
Enable Signal Map
When OELE is HIGH and BOE[x] is HIGH, the associated
Serial Driver is enabled. When OELE is HIGH and BOE[x] is
LOW, the associated driver is disabled and internally powered
down. If both outputs for a channel are in this disabled state,
the associated internal logic for that channel is also powered
down. When OELE returns LOW, the values present on the
BOE[3:0] inputs are latched in the Output Enable Latch, and
remain there until OELE returns HIGH to enable the latch. A
device reset (TRSTZ sampled LOW) clears this latch and
disables all output drivers.
Note
.
When all transmit channels are disabled (i.e., both
outputs disabled in all channels) and a channel is re-enabled,
the data on the Serial Drivers may not meet all timing specifi-
cations for up to 200
μ
s.
Transmit PLL Clock Multiplier
The Transmit PLL Clock Multiplier accepts a character-rate or
half-character-rate external clock at the REFCLK input, and
multiples that clock by 10 or 20 (as selected by TXRATE) to
generate a bit-rate clock for use by the Transmit Shifter. It also
provides a character-rate clock used by the transmit paths.
Table 8. TX Modes 5 and 8, Dual-channel Bonded (RXMODE[1] = HIGH)
S
T
T
T
T
Characters Generated
X
X
X
X
X
X
X
X
X
0
0
1
1
X
X
X
X
X
0
1
0
1
0
1
0
1
X
X
X
X
X
0
0
1
1
X
0
0
0
0
0
0
0
0
1
Encoded data character on channel A
K28.5 fill character on channel A
Special character code on channel A
16-character word sync on channel A
Encoded data character on channel B
K28.5 fill character on channel B
Special character code on channel B
16-character word sync on channel B
16-character word sync on channels A and B
BOE
Input
BOE[3]
BOE[2]
BOE[1]
BOE[0]
Output
Controlled
(OELE)
OUTB2
±
OUTB1
±
OUTA2
±
OUTA1
±
BIST
Channel
Enable
(BISTLE)
Transmit B
Receive B
Transmit A
Receive A
Receive PLL
Channel
Enable
(RXLE)
X
Receive B
X
Receive A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0201DXB-BBC | ULTRA-THIN SVGA CABLE 10FT MALE/MALE |
| CYP15G0201DXB-BBI | ULTRA-THIN SVGA CABLE 15FT MALE/MALE |
| CYV15G0201DXB | Dual-channel HOTLink II Transceiver |
| CYV15G0201DXB-BBC | Dual-channel HOTLink II Transceiver |
| CYV15G0404RB-BGC | Independent Clock Quad HOTLink Reclocking Deserializer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0201DXB_05 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Dual-channel HOTLink II⑩ Transceiver |
| CYP15G0201DXB-BBC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBXC | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0201DXB-BBXI | 功能描述:電信線路管理 IC Dual Channel XCVR 1.5Gbps Bckplane IND RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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