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參數(shù)資料
| 型號： | CYV15G0404RB-BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Independent Clock Quad HOTLink Reclocking Deserializer |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 27 X 27 MM, 1.57 MM HEIGHT, TBGA-256 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大?。?/td> | 580K |
| 代理商： | CYV15G0404RB-BGC |
PRELIMINARY
Independent Clock Quad HOTLink II Reclocking
Deserializer
CYV15G0404RB
Cypress Semiconductor Corporation
Document #: 38-02102 Rev. **
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised July 21, 2004
Features
Quad channel video reclocking deserializer
—195- to 1500-Mbps serial data signaling rate
—Simultaneous operation at different signaling rates
Second-generation HOTLink
technology
Compliant to SMPTE 292M and SMPTE 259M video
standards
Supports reception of either 1.485 or 1.485/1.001 Gbps
data rate with the same training clock
Supports half-rate and full-rate clocking
Internal phase-locked loops (PLLs) with no external
PLL components
Selectable differential PECL-compatible serial inputs
—Internal DC-restoration
Synchronous LVTTL parallel interface
JTAG boundary scan
Built-In Self-Test (BIST) for at-speed link testing
Link Quality Indicator
—Analog signal detect
—Digital signal detect
Low-power 3W @ 3.3V typical
Single 3.3V supply
Thermally enhanced BGA
0.25
μ
BiCMOS technology
Functional Description
The CYV15G0404RB Independent Clock Quad HOTLink II
Deserializing Reclocker is a point-to-point or point-to-multi-
point communications building block enabling transfer of data
over a variety of high-speed serial links including SMPTE 292
and SMPTE 259 video applications. It supports signaling rates
in the range of 195 to 1500 Mbps per serial link. The four
channels are independent and can simultaneously operate at
different rates. Each receive channel accepts serial data and
converts it to 10-bit parallel characters and presents these
characters to an Output Register. The received serial data can
also be reclocked and retransmitted through the reclocker
serial outputs.
Figure 1
illustrates typical connections between
independent
video
co-processors
CYV15G0404RB
Reclocking
CYV15G0403TB Serializer chips.
The CYV15G0404RB satisfies the SMPTE-259M and
SMPTE-292M compliance as per SMPTE EG34-1999 Patho-
logical Test Requirements.
As
a
second-generation
CYV15G0404RB extends the HOTLink family with enhanced
levels of integration and faster data rates, while maintaining
serial-link compatibility (data and BIST) with other HOTLink
devices.
Each channel of the CYV15G0404RB Quad HOTLink II device
accepts a serial bit-stream from one of two selectable PECL-
compatible differential line receivers, and using a completely
integrated Clock and Data Recovery PLL, recovers the timing
information necessary for data reconstruction. The recovered
bit-stream is reclocked and retransmitted through the
reclocker serial outputs. Also, the recovered serial data is
deserialized and presented to the destination host system.
Each channel contains an independent BIST pattern checker.
This BIST hardware allows at-speed testing of the high-speed
serial data paths in each receive section of this device, each
transmit section of a connected HOTLink II device, and across
the interconnecting links.
The CYV15G0404RB is ideal for SMPTE applications where
different data rates and serial interface standards are
necessary for each channel. Some applications include multi-
format routers, switchers, format converters, SDI monitors,
and camera control units.
and
Deserializer
corresponding
and
HOTLink
device,
the
Figure 1. HOTLink II System Connections
V
10
10
10
10
V
10
10
10
10
Serial Links
Independent
Channel
CYV15G0404RB
CYV15G0403TB
Serializer
Independent
Channel
Reclocking Deserializer
Reclocked
Outputs
Reclocked
Outputs
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