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參數(shù)資料
| 型號： | CYNSE70032-66BGI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Network Search Engine |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA272 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, BGA-272 |
| 文件頁數(shù)： | 110/126頁 |
| 文件大小： | 3333K |
| 代理商： | CYNSE70032-66BGI |
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CYNSE70032
Document #: 38-02042 Rev. *E
Page 110 of 126
15.8
The following explains the SRAM Write operation done via a table(s) of up to 31 devices and with the following parameters:
TLSZ = 10. The diagram of this table(s) is shown in
Figure 15-12
. The following assumes that SRAM access is accomplished
through CYNSE70032 device number 0 (the selected device).
Figure 15-13
and
Figure 15-14
show the timing diagram for device
number 0 and device number 30, respectively.
Cycle 1A
: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[21:19] on CMD[8:6] in this cycle.
Note
. CMD[2] must be set to 0 for SRAM Write,
because burst Writes into the SRAM are not supported.
Cycle 1B
: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
address, with DQ[20:19] set to 10, to select the SRAM address.
Note
. CMD[2] must be set to 0 for SRAM Write, because burst
Write
S
into the SRAM are not supported.
Cycle 2
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
Cycle 3
: The host ASIC continues to drive DQ[67:0]. The data in this cycle is not used by the CYNSE70032.
At the end of cycle 3, a new command can begin. The Write is a pipelined operation; however, the Write cycle appears at the
SRAM bus with the same latency as the Search instruction (as measured from the second cycle of the Write command).
SRAM Write with Table(s) Consisting of up to 31 Devices
cycle
1
CLK2X
CE_L
cycle
2
cycle
3
cycle
4
cycle
5
cycle
6
cycle
7
cycle
8
cycle
9
cycle
10
PHS_L
SADR[21:0]
SSF
SSV
1
0
0
CMDV
CMD[1:0]
CMD[8:2]
01
Write
A B
Address
DQ
z
WE_L
OE_L
0
ALE_L
z
z
ACK
x
x
1
0
1
1
z
1
1
z
1
TLSZ = 01, HLAT = XXX, LRAM = 1, LDEV = 1
Figure 15-11. SRAM Write Timing for Device Number 7 in a Block of Eight Devices
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